Failed Paths

[Altera_Forum]

Hi all, please can anyone explain me what is a failed path in the report of the timing analyzer?

[Altera_Forum]

--- Quote Start ---  Hi all, please can anyone explain me what is a failed path in the report of the timing analyzer?  --- Quote End ---    Hi,  that is a path, which violates the specified requirements. E.g. the required clock speed.  Kind regards  GPK

[Altera_Forum]

Thanks, 

I suppose the fitter place and route the design and then there is the timing analisys. If I have for example 100 failed paths the one routed is included in these 100 or the one routed is ok and there are other 100 paths failed? I am using the classic analyzer.  Best regards.   Stefano

[Altera_Forum]

--- Quote Start ---  Thanks, I suppose the fitter place and route the design and then there is the timing analisys. If I have for example 100 failed paths the one routed is included in these 100 or the one routed is ok and there are other 100 paths failed? I am using the classic analyzer.  Best regards.   Stefano  --- Quote End ---    Hi Stefano,  the timing analysis is done for all paths in your design. You can set the number of reported signals for the timing analyzer. The default is 100. All pahts which violates the requirement are marked in red. BTW: you should get an info in the message window about the number of failing paths.  Kind regards  GPK

[Altera_Forum]

You mean that for all possibly path in the design the is the analysis? I saw some reports where "from" and "to" are not directly connectd but through some logic. Wht does it mean an and hold violation of 5 ns if "from" and "to" are not directly connected?

[Altera_Forum]

--- Quote Start ---  You mean that for all possibly path in the design the is the analysis? I saw some reports where "from" and "to" are not directly connectd but through some logic. Wht does it mean an and hold violation of 5 ns if "from" and "to" are not directly connected?  --- Quote End ---    Hi,  the classic timing analyzer generates several reports:  Clock Setup : (clock_name) Clock Hold : (clock_name)   These are the timing results for all register-to-register paths in your design. When you have Clock Setup violation your design is too slow. Clock Hold violations are often caused by clock skew (e.g in case of gated clocks).  tsu + th:  This reports your input timing. The paths from the input pins to register.  tco:  This reports your output timing. The paths from registers to output pins.  tpd:   This is the so-called propagation delays, which describes the timing of paths without registers through your device.  Kind regards  GPK

[Altera_Forum]

So i undestand well every possible net in the design is analyzed by the timing analyzer and for every net are calculated the time parameters (hold for example). In the specified case of the hold violation If i hae a vilation of 5 ns it means that the delay from the "from" register to the "to" register there is a delay of 5 ns respect the edge of the clock of the "to" register. If some of these register do not have a direct connection but there is ome logic in the path this warning can be non so important. How I can identify which warnig is really important. My project is old and made without all the altera recomendation about clocking scheme and so on... 

 Tx and Best Regards.  Stefano

[Altera_Forum]

--- Quote Start ---  So i undestand well every possible net in the design is analyzed by the timing analyzer and for every net are calculated the time parameters (hold for example). In the specified case of the hold violation If i hae a vilation of 5 ns it means that the delay from the "from" register to the "to" register there is a delay of 5 ns respect the edge of the clock of the "to" register. If some of these register do not have a direct connection but there is ome logic in the path this warning can be non so important. How I can identify which warnig is really important. My project is old and made without all the altera recomendation about clocking scheme and so on...  Tx and Best Regards.  Stefano  --- Quote End ---    Hi,  is it a Clock Hold time vioaltion ? Can you please list one of the paths ?  Kind regards  GPK

[Altera_Forum]

Here one hold violation 

 -10.661 ns Address_Rx_Updated:inst28|inst14[0] de_staffatore_flip_1:inst42|inst56 RCLK RCLK 0.000 ns 14.645 ns 3.984 ns  All the two registers are clocked with the same clock RCLK, but the first register is a signal addressing a multipexer, the second is a register where i read a data passing through the same multiplexer.  How is important this?  Thanks.

[Altera_Forum]

--- Quote Start ---  Here one hold violation  -10.661 ns Address_Rx_Updated:inst28|inst14[0] de_staffatore_flip_1:inst42|inst56 RCLK RCLK 0.000 ns 14.645 ns 3.984 ns  All the two registers are clocked with the same clock RCLK, but the first register is a signal addressing a multipexer, the second is a register where i read a data passing through the same multiplexer.  How is important this?  Thanks.  --- Quote End ---    Hi,  it looks to me that you have a large clock skew, because your required P2P requirement is 14.645 ns.  Please select one row in the result tab, right mouse clock, choose "List Path".  Expand all "+" signs and post the result or attache it.  Kind regards  GPK

[Altera_Forum]

I have another question.. is possible to avoid the trasformationa of a group af DFF into memory. i tried several option but it always happes. 

  TX

[Altera_Forum]

--- Quote Start ---  I have another question.. is possible to avoid the trasformationa of a group af DFF into memory. i tried several option but it always happes.   TX  --- Quote End ---     Hi,  can you show what kind of registers are implemented as memory ? Shiftregisters ?  Kind regards  GPK