HiMy program runs fine on emulation, but running estimation fails. I would like to understand why I am getting this error:
Compiler Command: aoc -v --fp-relaxed --fpc -c ./device/Krnl_GA.cl --report Failed to map instruction style information: inst: switch i8 %mode.0280852, label %landing.landing.switch.else.if370 def id: inst switch llvm-type=<any> style: <default>(0) Compiler Warning: Auto-unrolled loop at /home/wimi/lvs/ofdock_altera/ofdock_taskpar_alt//home/wimi/lvs/ofdock_altera/ofdock_taskpar_alt/device/auxiliary_genetic.cl:411 ******* Error: Assert failure at InstStyleInfo.cpp(64) ******* Failed to map instruction style information. style_def != 0 FAILED 0 libLLVM-3.0.so 0x00007fa432290fbf 1 libLLVM-3.0.so 0x00007fa432292f32 2 libpthread.so.0 0x0000003e7b00f7e0 3 libLLVM-3.0.so 0x00007fa43296b71d acl::evaluate_style_info(llvm::Instruction const*, acl::InstStyleInfo*, bool, llvm::Pass*, llvm::TargetData*) + 701 4 libLLVM-3.0.so 0x00007fa43354b44e acl::InstStyleInfoCache::get_style_info(llvm::Instruction const*, bool) + 286 5 libLLVM-3.0.so 0x00007fa4334c252f acl::BasicBlockHwDependency_impl::BasicBlockInfo::build_delay_info() + 367 6 libLLVM-3.0.so 0x00007fa4334cf21b acl::BasicBlockHwDependency::runOnFunction(llvm::Function&) + 75 7 libLLVM-3.0.so 0x00007fa432b8f06f llvm::FPPassManager::runOnFunction(llvm::Function&) + 527 8 libLLVM-3.0.so 0x00007fa432b8f1d0 llvm::FPPassManager::runOnModule(llvm::Module&) + 80 9 libLLVM-3.0.so 0x00007fa432b8eb91 llvm::MPPassManager::runOnModule(llvm::Module&) + 577 10 libLLVM-3.0.so 0x00007fa432b8ed3b llvm::PassManagerImpl::run(llvm::Module&) + 187 11 aocl-opt 0x000000000041956d main + 4781 12 libc.so.6 0x0000003e7a81ed1d __libc_start_main + 253 13 aocl-opt 0x000000000040cd49 Stack dump: 0. Program arguments: /opt/cad/altera/altera-16.1/hld/linux64/bin/aocl-opt --acle ljg7wk8o12ectgfpthjmnj8xmgf1qb17frkzwewi22etqs0o0cvorlvczrk7mip -board /opt/cad/altera/altera-16.1/hld/board/a10_ref/hardware/a10gx/board_spec.xml -fp-relaxed=true -fpc=true -dbg-info-enabled Krnl_GA.1.bc -o Krnl_GA.kwgid.bc 1. Running pass 'Function Pass Manager' on module 'Krnl_GA.1.bc'. 2. Running pass 'Basic block hardware dependency analysis' on function '@Krnl_GA'According to the log, the problem is within a switch case statement, but I have no idea why it is failing. Anyone can give me some hints?
Your code is probably too complex for Altera's compiler, I would specifically advise against using large switch/case blocks. If you expect the switch/case block to be implemented as an FSM by the compiler (like it would in HDL), it will most likely not happen; instead, the compiler will probably try to pipeline the operation by creating a different path for each case statement and then insert extra registers to unify the latency of all the paths.You should report compiler crashes like this directly to Altera, they are the only ones who can tell you what is wrong. P.S. If you are reporting it to Altera, don't forget to include the "defines.h" file so that they can reproduce the crash.
Thanks for the useful reply.Could you tell me please how I report directly to Altera? I am new to this tool, so no idea how to do it. Any link would be really appreciatted.
Got to this address:https://www.altera.com/mal-all/mal-signin.html (https://www.altera.com/mal-all/mal-signin.html) Create a new account, log in, got to "mySupport" and create a support request and explain your problem, submit it, then attach your .cl and .h files to the request (you can attach files only after submission) and wait for somebody to reply to you.