Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Fifo memory IP Core generating recovery violations


I have a problem with the Fifo memory IP Core and the Recovery and Removal Timing analysis. The Fifo core uses the Avalon-MM Write Slave to Avalon-ST Source interface and with the Backpressure activated.

In qsys system I included this ip core using the standard megawizard. The (Avalon-MM) wrclk is 50 MHz and the rdclk is approx 122 MHz.

Both clocks come from different plls and are routed through reset_synchronizers. The timing analysis returns unfortunately recovery violations in more or less 20 paths from rdclk reset_synchronizer output to aclr input of several registers in the dcfifo instance (inside of Fifo memory core) and from wrclk to another aclr input.

I read in the literature, that explains:


"You may safely ignore warnings that represent transfers from aclr to the read sideclock domain. To ensure that the design meets timing, enable the ACLR synchronizer for both read and write domains. To enable the ACLR synchronizer for both read and write domains, on the DCFIFO 2tab of the FIFO Intel FPGA IP core, turn on Asynchronous clear, Add circuit to synchronize ‘aclr’ input with ‘wrclk’, and Add circuit to synchronize ‘aclr’ inputwith ‘rdclk’."

Page 19


Unfortunately i don't have the possibility to turn on the asynchronous clear in the dcfifo using the megawizard for the fifo memory ip core.

Is this a problem that i can ignore using set_false_paths in the .sdc file?

Attached the recovery reports from rdclk to wrclk and vice-versa.

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