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Beginner
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Fitter errors trying to convert old qpf to newer quartus/device

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Hello,

I found code for a RISC-V core implementation, which is supposed to be optimized for FPGA use, Orca by VectorBlox. VectorBlox was bought out by Microchip, and their original Orca repository no longer exists, but this repository appears to be a clone of it: https://github.com/riscveval/orca-1 

There are sample builds for a few different FPGA vendors including Altera (intel): https://github.com/riscveval/orca-1/tree/master/systems/de2-115 

Those build instructions target a Cyclone IV FPGA with Quartus 15.0. I am trying to convert the project to an Arria 10 with Quartus 19.2.

Generating the HDL with Platform Designer (Qsys) seemed to work fine after automatically converting to an Arria 10 target. However, when trying to compile, the fitter has been getting stuck, seemingly due to various set_global_assignment calls in the system.qsf file. 

First was MAX_CORE_JUNCTION_TEMP; the original value of 85 threw a fitter error, as it wasn't supported, so I changed it to 100 to get past it. 

Next was "I/O standard 2.5 V is not supported for selected device family" (ID: 119028), which I tried to adjust through the pin options voltage page (based on this: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs.htm ), but that didn't do anything, so I changed another line in the system.qsf: 'set_global_assignment -name STRATIX_DEVICE_IO_STANDARD' from 2.5 V to 1.8 V (based on the options from the voltage page above), which got me past that error. 

 

Now I am stuck with the error "Some pins have illegal board trace models." (ID: 329006), which itself contains over 100 of error ID: 20403, both "Global setting for OUTPUT_IO_TIMING_NEAR_END_VMEAS is not supported. Please use this setting with pin assignments." and the same but with ..._FAR_END_VMEAS. I see another set_global_assignment related to this in the system.qsf file here:

orca-1/systems/de2-115$ grep -ni 'OUTPUT_IO' system.qsf
116:set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
117:set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
118:set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
119:set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

 

Continuing on this path, how could I get past this error?

 

Conversely, is there a better way for converting from an old qpf for an old device to a newer device/quartus? 

I'm sure my hacks so far are not standard practice, so any suggestions would be appreciated. Thanks!

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Employee
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Hi Ryan

Sorry for late response. 

Can you try to remove those board trace model assignment with OUTPUT_IO_TIMING_NEAR_END_VMEAS and OUTPUT_IO_TIMING_FAR_END_VMEAS? Those assignment might not supported by certain devices.

Cross family device migration has no direct flow. We have to review from various aspect such as pin assignment, IP migration, parameter setting and etc. The suggested migration is vertical migration within the same family which can be referred to datasheet of each family.

 

Thanks.

Eng Wei 

 

 

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Is-there-a-known-good-project-i-can-use-...

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Employee
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Hi Ryan

Sorry for late response. 

Can you try to remove those board trace model assignment with OUTPUT_IO_TIMING_NEAR_END_VMEAS and OUTPUT_IO_TIMING_FAR_END_VMEAS? Those assignment might not supported by certain devices.

Cross family device migration has no direct flow. We have to review from various aspect such as pin assignment, IP migration, parameter setting and etc. The suggested migration is vertical migration within the same family which can be referred to datasheet of each family.

 

Thanks.

Eng Wei 

 

 

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Is-there-a-known-good-project-i-can-use-...

View solution in original post

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Employee
64 Views

Hi Ryan

To add on, referring to 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/rn/rn_qts_dev_support_updat...

Section 2.1 mentioning that these 2 assignments cannot be set as global setting. You can still use these assignments as pin assignments.

Thanks.

Eng Wei

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Beginner
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Thanks for the response! 

Commenting out those lines in the .qsf did allow compilation to finish.

However, I was hoping to get an estimation of Fmax in the timing reports, but they state there are "no paths to report." The clock status summary shows an unconstrained clock called clock_50. There are a few warnings associated with clock_50 in the Timing Analyzer messages, including message IDs 332174, 332049 and 332060. The gist of these messages is essentially: "clock_50 could not be matched with a port", "ignored create_clock" and "clock_50 was determined to be a clock but was found without and associated clock assignment", respectively. 

Do you have any suggestions for "constraining" this clock and producing an Fmax estimation? 

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Moderator
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You have to create a .sdc file that defines, at a minimum, the clocks and external I/O timing of the design.  To learn about timing analysis and the timing analyzer, start here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

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