Hello,I am creating a Quartus project to transmit high-speed data using the Arria 10 Transceiver Native PHY. I am supplying the the serial clock (at 1.5GHz) to the tx_serial_clk0 using Arria 10 Transceiver ATX PLL which generates 1.5GHz clock using input 150MHz clock. I am creating this 150Mhz clock using another PLL (Altera IOPLL) that takes the 50MHz FPGA clock as the input. I have attached the qsys design screenshot of the project. The compilation of the design is successful. However, the fitter prompts an error which I am not able to understand. The error prompt is: Error (11192): Input port "REF_IQCLK" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" cannot connect to PLD port "OUTCLK" of "IOPLL" for atom "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopll_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst". Extra Info (13133): Output port's "OUTCLK" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopll_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst". Extra Info (13134): Input port's "REF_IQCLK" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_xcvr_atx_pll_a10_171_7s4kdty:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_hssi_pma_lc_refclk_select_mux_inst". Extra Info (12879): Input port "REF_IQCLK" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" can connect to: Extra Info (12880): Port "O_REFCLK_A" of "HSSI_REFCLK_DIVIDER" It basically says that I cannot provide the output of the IOPLL to the pll_refclk0 of the ATX PLL. But, the ATX PLL needs reference clock of 150MHz. It does not make sense to me. Please help. Thank you
I am having a similar problem, the IOBUF/O output can't be connected to the CMU_FPLL_REFCLK_SELECT/REFCLK input
can I add BUFCLK/BUFCLKBLOCK to my design manually?
other suggestion is maybe to instanciate HSSI_REFCLK_DEVIDER, which I did not find.
Are you using a template or an example? or your own design?
Because in my case I used an Arria 10 Transceiver example and discover that is was a wire issue.
In the example, two signals were exportered from the top level design and connected together in the testbech. So instead of exporting them, I contected them together in the top level.