Flash interface problem

[Altera_Forum]

Hi everybody, 

I am trying to burn my design in to the on-board Flash but there are a couple of things that I cant understand.  The Stratix II (EP2S60ESF672C5) development board that I have got uses AMD AM29LV128M Flash memory. So as per the instructions given in the manual, I have added a CFI controller and the MM Tristate Bridge in the SOPC builder design. As expected the address, data, Rd/Wr and CS ports appear as unassigned pins in the Quartus II design.  problem: I am pretty sure that I have to assign these unassigned ports to some Stratix II device pins but the reference manual has no info saying which data/address line goes to which Stratix II pin. It only says that it is connected to a shared-bus and that by "using sopc builder, designers can interface a nios ii processor system to any device connected to the off-chip shared bus"  a) AM I right to think that these data/address lines are not auto connected by the SOPC builder and have to be assigned to the Stratix II device pins using Assignment -> pins?  b) I have attached the shared-bus document with this post, any suggestions regarding this would be highly appreciated !!  Thanks in advance.

[Altera_Forum]

ooops... forgot to attach the shared bus table ! The table as you can see has no info regarding the Stratix II device connections !

[Altera_Forum]

a) AM I right to think that these data/address lines are not auto connected by the SOPC builder and have to be assigned to the Stratix II device pins using Assignment -> pins? 

 Yes, you are right and you have to. Your assignments have to be consistent with physical pin connections on the dev board. You can find the physical pin connections of the board from the user manual or user guide of the dev board.