Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17252 Discussions

Trouble simulating multiple verilog files

Altera_Forum
Honored Contributor II
‎05-21-2009 06:15 PM
1,365 Views

Hi there! 

 

I'm running ModelSim Altera Web Edition and having a bit of trouble simulating multiple Verilog files. 

 

I have a 'top' module that uses and connects the modules of the other Verilog files. The simulation files is also generated from a Quartus II (also free edition) ... I have no problem simulating with just one Verilog/VHDL file. 

 

Any restrictions that make this kind of trouble? 

 

Thanks for your help!
0 Kudos

Link Copied

3 Replies
Altera_Forum
Honored Contributor II
‎05-21-2009 06:42 PM
523 Views

there are no restrictions like that. in fact between a testbench and DUT there are already multiple Verilog files involved in the simulation.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎05-21-2009 07:03 PM
523 Views

Okey, 

 

Any simple howto tutorials you can give me? 

 

I have looked on this thread: 

http://www.alteraforum.com/forum/showthread.php?t=3707
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎05-21-2009 07:06 PM
523 Views

I think I found a major flaw in my code ;) 

 

Hah :p I will look on this first! 

# Update: 

1. Didn't help :mad:
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.