Force a reg not to use M9K but logic

[Altera_Forum]

Hi 

 I do use M9K for ROM tables and this works fine I also have to use quite some latches since I works as pipeline  The problem are when I do use latches then QuartusII on some of the latches do use M9K and other a logic , then I do not have enough M9K for ROM  I have tried different combination with ramstyle="logic" in my verilog  (* ramstyle = "logic" *) reg [63:0] Block_out; reg [63:0] Block_out /* synthesis ramstyle = "logic" */;  And still some of my reg do use M9K  Any hint?

[Altera_Forum]

There are different synthesis attributes to control RAM inference for memory arrays and for shift registers. Apparently your construct refers to the latter. http://www.alteraforum.com/forum/showthread.php?t=37702

[Altera_Forum]

That did the trick 

Assignments -> settings -> analysis and synthesis settings -> more settings  "auto shift register placements". Change this to "off". Thank you

[Altera_Forum]

A global assignment works too, of course. As in the linked thread, the assignment is often required for specific objects.