What FREE tools are available for synthesis and simulation?FREE means: *gratis (no cost) *license (if required) lasts forever; never expires *license cannot be tied to hardware *anybody and everybody can get and use the tool *could be closed source, but prefer open source *must run on Linux *must be statically linked to avoid library issues in the future I want to play around with SoC architectures making high-bandwidth data radios for amateur radio. If it is a hassle to get the tools, or if there are any financial costs, no large community will develop as it has in the Linux world. So it must meet all of the requirements listed above. I'm willing to pay for hardware, but not software. This is for a hobby: amateur radio. If there are any such tools that meet these requirements, then what limitations do they have? Thank you, Ken Hendrickson PS As long as FPGA manufacturers charge money for their software tools, there will never develop a maker community experimenting with them as a hobby.
--- Quote Start --- What FREE tools are available for synthesis and simulation? FREE means: *gratis (no cost) --- yes, the intel/altera 'lite' edition is completely free to download -- see https://www.altera.com/downloads/download-center.html. similar for xilinx and lattice devices *license (if required) lasts forever; never expires --- not applicable, no license required *license cannot be tied to hardware --- not applicable, no license required *anybody and everybody can get and use the tool --- depends, some countries may be subject to export restrictions, like dprnk. read the fine print *could be closed source, but prefer open source --- all tools i know of for fpga layout are closed source, as the very low level device architecture info is proprietary *must run on Linux --- most do, like altera tools, but are 'officially supported' only on specific linux distros and releases. the tools are precompiled, no sources available. *must be statically linked to avoid library issues in the future --- i am not sure you get a choice on this, most likely not in my experience. see my previous comment. I want to play around with SoC architectures making high-bandwidth data radios for amateur radio. If it is a hassle to get the tools, or if there are any financial costs, no large community will develop as it has in the Linux world. So it must meet all of the requirements listed above. I'm willing to pay for hardware, but not software. -- i daresay that the current fpga development community probably dwarfs the number of amateur radio sdr developers/users by a factor of 10x. a lot of these are low end developers and university student projects, as well as electronics hobbyists. there are already lots of fpga-based sdr radios available both as commercial products and hobbbyist/open-source projects. This is for a hobby: amateur radio. If there are any such tools that meet these requirements, then what limitations do they have? Thank you, Ken Hendrickson PS As long as FPGA manufacturers charge money for their software tools, there will never develop a maker community experimenting with them as a hobby. --- as i mentioned above, all major fpga device developers offer a fully free design environment that supports, for the most part, their low end and medium density fpga devices. if you want to experiment with state of the art bleeding edge devices expect to pay for the tools.
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My comments inline, above, in bold. Don AK6DN
Altera offers the Lite edition for free, but this will always be the lower end of the cheaper devices (arrias, cyclone and MAX). You also will not have access to many IP cores (For example, I think PCIe and Ethernet IP cores are excluded).These tools will never be open source, and because of the massive task in fitting information (and probably propriatery and secret) on how to actually fit logic onto a device, there likely never will be. So you will have to take what you are given if you want to get into the FPGA world. --- Quote Start --- PS As long as FPGA manufacturers charge money for their software tools, there will never develop a maker community experimenting with them as a hobby. --- Quote End --- Maybe not, but this will not bother the $5bn dollar companies xilinx and altera. Hobbiest buy chips in singles. They are far more interested in the companies that buy them in the 1000s
@Tricky,I don't get over to these forums much, perhaps I should more often. That said, I am working within an open source FPGA community that you might wish to be aware of.
- Most of my work revolves around yosys (http://www.clifford.at/yosys/). yosys (http://www.clifford.at/yosys/) is a free/open source synthesizer. It does have preliminary support for Altera parts, just ... not yet enough to build my own projects (https://github.com/zipcpu/arrowzip/). It currently does quite well with iCE40 designs, and I expect it will handle Xilinx 7-series designs soon enough. There's just no one working on the Intel back end right now. (Hear that, Intel? We'd love to have you help out, rather than to have Xilinx be the first major FPGA chipset we support ... there's still time!)
- yosys (http://www.clifford.at/yosys/) can produce outputs in many formats, including a variety of ASIC formats as well.
- yosys (http://www.clifford.at/yosys/) can also output your design in a number of formats necessary to formally verify the design using a variety of free formal solvers. This is how I have been using it recently: as a front end for formal verification (http://zipcpu.com/blog/2017/10/19/formal-intro.html). Checkout symbiyosys (https://symbiyosys.readthedocs.io/en/latest/) if you are interested, or even this article (http://zipcpu.com/blog/2018/03/10/induction-exercise.html) for an example of how to use it.
- I have done all of my simulation work using verilator (http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html). verilator (http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html) is another free and open source tool, this time one that converts Verilog (or system verilog) to C++. I've then used that C++ quite successfully to drive co-simulations of my design(s) with hardware simulators (http://zipcpu.com/blog/2017/06/23/my-dbg-philosophy.html) for all of the hardware on the boards I am working with: flash, SDRAM, uarts (https://github.om/zipcpu/wbuart32), and even vga simulation (https://github.com/zipcpu/vgasim/)
- I've also been working on slowly building up a library of free and open source ip components (https://github.com/zipcpu). You can find it on my github page. (https://github.com/zipcpu) Some highlights include ...
- The zipcpu (https://github.com/zipcpu/zipcpu) is a free and open source CPU that can be used in place of many other proprietary CPU's out there. You do get what you pay for, though ... while I have full gcc+newlib (https://github.com/zipcpu/zipcpu/tree/master/sw) support for the zipcpu (https://github.com/zipcpu/zipcpu), I don't yet have gdb support and the zipdbg debugger is not a source level debugger. Linux support has been a goal for years, but although the hardware is just about there the software is far from ready.
- I've put together a series of posts on dsp filtering (http://zipcpu.com/dsp/dsp.html), describing not only several different filters (https://github.com/zipcpu/dspfilters/) but also how you might test them (http://zipcpu.com/dsp/2017/12/06/fastfir-tb.html). Many of these are built for high speed, high bandwidth applications, but I did spend some time discussing how to build a slower filter (http://zipcpu.com/dsp/2017/12/30/slowfil.html) as well.
- There's also a discussion of several methods of generating sine/cosine waves (https://github.com/zipcpu/cordic/) on the blog as well--to include a description of how to build and test (http://zipcpu.com/dsp/2017/10/02/cordic-tb.html) a cordic (http://zipcpu.com/dsp/2017/08/30/cordic.html) of arbitrary size. A waiting article will discuss how to generate a better quality sine wave with only two multiplies.
- There's a discussion of how to build a numerically controlled oscillator (http://zipcpu.com/dsp/2017/12/09/nco.html), or even a digital phase lock loop (http://zipcpu.com/dsp/2017/12/14/logic-pll.html)
- I also try to be responsive to my patreon supporters (https://www.patreon.com/zipcpu) (there aren't that many of them yet), so if these are topics you are interested in then please feel free to support my work (https://www.patreon.com/zipcpu). Every donation goes a long ways, even the smallest ones
- My focus has always been how to get the most out of your fpga (http://zipcpu.com/blog/2017/06/12/minimizing-luts.html) $'s, since I'm sure you (like me) want bleeding fast performance without paying the pocket book costs required to get it. This also places a different focus on open source IP when compared with the proprietary IP: open source IP is focused on getting the most capability from the board you've already paid for, proprietary vendor supplied IP has no such limitations. Indeed, it's no skin off Intel or Xilinx's back if their IP is too big to fit on your chip, they'd rather you bought the most expensive chip anyway.
Finally found the quote I was missing ... from olof's twitter feed (https://twitter.com/olofkindgren), "Closed source soft CPUs are the worst of two worlds. You have to worry about resource use and timing without being able to analyze it".I also found my rant (https://forum.digilentinc.com/topic/4472-rants-about-fpga-tool-chains/) comparing the way open source toolchain's are supported vs how vendor supported tool chains are supported. You can read about that here (https://forum.digilentinc.com/topic/4472-rants-about-fpga-tool-chains/) if you would like. The post and replies were actually rather fair and balanced (IMHO).
Let's be honest, the status of the closed source FPGA vendor tools is pretty abyssmal. I've had more experience with Vivado than Quartus, but I hear bad things from that side as well. At some point Xilinx even disabled bug reports unless you were a "tier 1" customer - they didn't even want to get our bug reports because we were small fry. When I was doing FPGA development with Vivado it seemed like much of our effort was spent working around bugs.I had hopes that maybe when Intel bought Altera they'd pour more resources into the FPGA tools. Not sure if that's happened or not. I tried to use the Quartus OpenCL (free download) tool from Intel/Altera a couple of months back and gave up because of some licensing issue I kept running into (I was working from a tutorial where the first step was "Download the free OpenCL tool"). Life's too short to chase a licensing bug for a "free" tool. Actual free open source tools like Yosys allow users to look into the source code if need be. Or to submit issues to the developers on github. A lot of us have dreamed of a fully open source synthesis tool that could get us from HDL->bitstream for years and now it seems to have arrived (at least for some Xilinx 7 parts and Lattice ICE40). The other day I got my BlackIce II board (fully open source board) with a Lattice ICE40 FPGA and used Yosys to get a fully open RISCV core running on it. It worked. I was elated. No closed source software involved - this is an amazing era we're entering. I really wonder what Intel/Altera gains from keeping their tools licensed (as in there's a license manager)? Selling Quartus licenses is a tiny drop in Intel's revenue stream - why bother? I'd argue that making all the Altera dev tools completely free (free from licensing, not necessarily even open source) would be a good move for them. Ultimately they're trying to sell chips. And since they're trying to make it a lot easier for software developers to target FPGAs seamlessly they should make those tools license-free as well (OpenCL synth) in order to get as many developers on board as possible. Even if Quartus itself isn't ever open sourced, perhaps Intel/Altera could open up the specs for the bitstream formats so that an open source ecosystem of tools could bloom around Altera FPGAs? This would benefit everyone including Intel/Altera.
Well done guys, keep up the good work.Although, being realistic, it will take A LOT to disrupt this market. Until it gets mainstream company support, things like this are constanly in danger of dying through lack of support and updates. Open source often is only really open to those technically able, or have the time to investigate. Companies cannot usually afford the man hours to use something like this. Big companies are using VHDL 2008, System Verilog 2012, UVM (as well as other open source libraries like OSVVM, UVVM), then there are all the tools promoting the virtues of Python for Verification and HDL generation. It feels rather fractured. These open source tools are A LONG way from gaining mainstream adoption.