Intel® Quartus® Prime Software
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Frequency variation in Quartus II with block diagram programming

Altera_Forum
Honored Contributor II
1,880 Views

Hi guys, 

 

I am facing problem in varying frequency of a square wave signal in block diagram way of programming. Find the schematic of the block diagram in the Attachment. Pls suggest the necessary modifications to have a frequency of (40 khz) in the circuit. 

 

 

--  

Sumanta Kumar Show 

 

 

Research Scholar 

E&E Dept. 

NITK Surathkal 

Karnataka, India
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Altera_Forum
Honored Contributor II
1,166 Views

I am able to generate square wave signal having frequency of (4.8 kHz). But I need to increase it to (40 kHz). Please suggest me the change needed to do in the Block diagram programming. 

 

--  

 

 

with regards 

Sumanta Kumar Show 

Research Scholar 

E&E Dept. 

NITK Surathkal 

Karnataka, India
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Altera_Forum
Honored Contributor II
1,166 Views

Hey Guys, 

 

Please have some response if you are familiar with the same problem of increasing frequency in FPGA as i have already mentioned. Its very urgent for me. Thanks in advance. 

 

 

 

 

--- Quote Start ---  

I am able to generate square wave signal having frequency of (4.8 kHz). But I need to increase it to (40 kHz). Please suggest me the change needed to do in the Block diagram programming. 

 

--  

 

 

with regards 

Sumanta Kumar Show 

Research Scholar 

E&E Dept. 

NITK Surathkal 

Karnataka, India 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
1,166 Views

Did you review the blurred picture in your post? How can you expect an answer referring to it?

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Altera_Forum
Honored Contributor II
1,166 Views

 

--- Quote Start ---  

Did you review the blurred picture in your post? How can you expect an answer referring to it? 

--- Quote End ---  

 

 

I will explain the logic which is given in the picture. 

 

Actually I need to generate a square wave output (0 - 10) volts in Block diagram programming. The schematic of the description is as below: 

 

1) The Internal clock is used to generate the Ramp signal. 

2) The Ramp is compared with a constant to generate square wave signal. 

3) Pin settings are done for 11 outputs of the DAC. 

 

My Cyclone II Altera chip (EP2C70F672C8) has Internal clock frequency of (400 MHz) which is able to produce a square wave output of (12 kHz) max. But I need (40 kHz) square wave signal. 

 

Pls provide with your suggestions for the above problem.
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Altera_Forum
Honored Contributor II
1,166 Views

Dividing 400 MHz by 10000 (ramp counting from 0 to 9999) will achieve the intended frequency.

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