Frozen counter

[Altera_Forum]

Hello :D, 

 I have spent some time trying to get the grip on Verilog by doing some counting, only the output is not quite as expected..Just a frozen on block of leds. If someone would like to check out my Quartus file, and tell me what I did wrong i'd be much obliged.  Also why are clock signals other than std logic square waves? I can't seem to figure out why the synthesizer assigns "clocks" to them?

[Altera_Forum]

How fast is your clock? Functionally it looks ok, but only ok - it could be better - but that's why you're here... 

 Your code is incrementing the count value displayed on your LEDs every 568 clock cycles. Even if you were running at 10MHz your 8-bit count would wrap every 14ms. You're not likely to see that.  As for the synthesizer creating clocks from your code - the 'clock' input to your 'Clockgenleach' module is driven by the 'true' signal from the previous module. You're using a register output to clock another register. So, the synthesizer has correctly identified the signal as a clock.  I'd like to recommend you recode the last block to look more like your 'clkif' block. Take the clock into it too and look for 'true' to be active on every clock cycle (rather than using 'true' to clock your register). That's much better synchronous design practice.  Cheers, Alex

[Altera_Forum]

Thanks! Got it working using the else if statement and lowering the frequency down a lot.  

Im planning on doing audio with it, so I wanted to make a general clock running outside some oscillators "running at 50Mhz / 88,2Khz = ~567 samples per sample"   But in clocking it all every cycle, isnt it tight and hot vs cool and loose processing then.. Or is it general bad practice to do so?   Edit: Heres a file to go with..

[Altera_Forum]

Glad to hear something's working. 

 Clocking a device 'every cycle' is common practice and perfectly acceptable. The heat generated/power consumed will will be a function of how many and how frequently registers actually toggle. You clock a device at 200MHz+ but if no registers actually change state you'll not consume much more power than an unconfigured device.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  Glad to hear something's working.  Clocking a device 'every cycle' is common practice and perfectly acceptable. The heat generated/power consumed will will be a function of how many and how frequently registers actually toggle. You clock a device at 200MHz+ but if no registers actually change state you'll not consume much more power than an unconfigured device.  Cheers, Alex  --- Quote End ---    Haha, yess. I was all like something I did works? Tweaked the middle if statement to go every "negedge" and did a sample and hold generator on the higher frequency for a little pseudo random generator :D  But I see, its kinda counter intuitive codewise but keeping up a transistor takes some energy as well, right.

[Altera_Forum]

Keeping a transistor on (or off) does consume some (very small amount of) energy, yes - but nothing as compared to the power dissipated when a register toggles. That's when your PSU will earn it's keep. 

 Cheers, Alex