Slave BFM not responding

Altera_Forum · ‎05-09-2013

Alright guys. So I've got a custom IP Avalon MM Master and I'm trying to check that it is implementing the avalon interface correctly. I've got it set up in a simulation with a slave BFM but while the signals seem to be going across to the BFM, it isn't responding... at all. I want to make sure I'm calling the APIs the correct way. Below is some simplified code showing the BFM APIs relative to other stuff. Note that this is a non-bursting simple setup so going between the two we only have address, read data, write data, byte enable, read, write, wait request (going off memory but I think thats right). I was expecting to see the slave assert wait request, pausing the transaction and then send back data (for the read), but I'm not seeing ANYTHING from the slave.

also if anyone knows of example code for an MM slave bfm, a link would be super helpful. I've heard one exists but all I've found is MM masters and ST slaves. Thanks guys!

`timescale 1ps/1ps
`define VERBOSITY VERBOSITY_INFO
`define BFM dut.slave
module SimScript();
  import verbosity_pkg::*;
  import avalon_mm_pkg::*;
  //stuff
  initial begin
  set_verbosity(`VERBOSITY);
  `BFM.init();
  
  //Write Process
  //prepare a BFM response to a stimulus
  `BFM.set_response_request(REQ_WRITE);
  `BFM.set_interface_wait_time(1,1);
  `BFM.push_response();
  //stimulus from custom IP goes out
  while(`BFM.get_response_queue_size()!=1)
    @(posedge clk);
  `BFM.pop_command;
  //this no information attempted to pull from BFM for write
  //Read Process
  //prepare BFM response
  `BFM.set_response_request(REQ_READ);
  `BFM.set_response_data(32'h01234567,0);
  `BFM.set_interface_wait_time(1,0);
  `BFM.push_response();
  //stimulus heads out
  while(`BFM.get_response_queue_size()!=0)
    @(posedge clk)
  `BFM.pop_command;
  RecievedData = `BFM.get_command_data(0);
endmodule

Altera_Forum · ‎05-15-2013

Update:

For those of you interested or having a similar problem..

I think the problem is not so much in the code posted here. To set this up after using msim.setup, devcom com, the simulation script is brought in the with the following statement

vlog -sv C:/<pathway>/SimScript.sv -L slave

the -L is apparently to make the systemverilog work, but I fear that pulling the packages from the slave (the custom IP does not seem to produce these files in the library) is not actually giving the master the ability to send its master signals out to the world. As a result, the BFM isn't responding at all because it doesn't know its being asked to respond, despite the fact that I can see my master trying to request a read/write. I have no idea how to fix this, but this is my current theory. Any advice on this would be appreciated.

Altera_Forum · ‎11-13-2014

Hello lucigen,

Even I am facing a same issue where I have a custom Avalon-MM Master Core with read logic. I created a Qsys project with clock & Reset source and custom core and generated the testbench. The testbench includes slave BFM for the master core. In BFM, I could able to receive read command request but when set response_data and do push_response, data is not seem to appear on master read port. The problem is as similar as you stated in 1st thread. Did you find any workaround/fix?