GX Transceiver pin assignment

[Altera_Forum]

Hi, 

 I am designing a data acquisition board with an ep4cgx50cf23 communicating with 2 AD9222 (ADC) , one 88E1111 (ETH) and an afbr-703sdz (optical transceiver from Avago).  The signals needed to connect with the Opt. Transceiver are :   TxD, RxD (CML standard) SDA, SCL, MOD_ABS, RS0, RS1, RX_LOS, TX_ DIS, TX_FAULT (3.3 V)  All the I/O needed are listed in the PORT section of my VHDL entity but the architecture part is empty as the code will be written later. In order to fix once for all the I/O pins of my cyclone device before manufacturing the PCB I am using the assignment editor to place the I/O.  my problem :  The TxD and RxD signals must be connected to the GXB dedicated pins but I can't find a way to assign them neither with the Pin Planner nor the Assignment editor ...  If I choose an I/O standard 1.5-V PCML for the TxD output I have this error : Error: Can't place pin OPT_TD with differential I/O standard -- no legal location available on target device  If I choose an I/O standard 1.5-V PCML and I try to force it on pin F2 (GXB_TX3P), I have this error :  Error: Differential I/O output pin OPT_TD is assigned to a non differential location F2. However, it must be assigned to a differential output location  Do you have any suggestions on how I can assign these specific I/O, without implementing an ALT_GX megafunction?

[Altera_Forum]

--- Quote Start ---   Do you have any suggestions on how I can assign these specific I/O, without implementing an ALT_GX megafunction?  --- Quote End ---    On the Stratix IV GX, you cannot place a GXB pin without having an ALT_GX megacore. I suspect the same goes for the Cyclone IV. I find that very annoying!  Cheers, Dave