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Gate level simulation problem in Modelsim while using Verilog output for Cyclone

Altera_Forum
Honored Contributor II
‎08-04-2011 06:37 AM
2,317 Views

I am using Cyclone IV E, ModelSim 6.6d and Quartus 11.0. 

I am using Verilog output format for the netlist writer. 

Modelsim opens correctly for RTL simulation but for gate level simulation there are errors "including" some library files. 

Each time these libraries need to be manually added. 

Is there a workaround?
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Altera_Forum
Honored Contributor II
‎08-04-2011 11:12 AM
1,587 Views

Add -L cycloneiv_ver -L altera_ver to your vsim command.

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