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15388 Discussions

Gated clock conversion fails due to memory

Alexander_Kobler
401 Views

Hello Intel community,

We use "set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON" for our prototyping system, which contains several memories (RAM, ROM). Up to now, this worked as expected. 

With a new component, which requires an additional RAM block, clock gate conversion fails, reason is "memory in the gated clock tree". The newly introduced memory is also listed in the mapper reports, section "Registers Packed Into Inferred Megafunctions", while all other memories are not listed here!?

Does anybody has a suggestion, how to fix this problem?

 

Thanks & best regards,

Alex

0 Kudos
1 Solution
Alexander_Kobler
269 Views

Hi,

 

Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)

 

But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC

Instead of:

 

  wire s_wen;
  assign s_wen = (~CEN) ? WEN : 1'b1;

 

Changed to:

 

wire [1:0] s_wen;
assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};

 

 

See also attached files.

 

Regards

View solution in original post

8 Replies
sstrell
Honored Contributor III
368 Views

The simplest (and best) solution would be to not gate your clocks.  Manually put that logic on local enables or on the enable of a clock control block instead.

Alexander_Kobler
365 Views

As already described, this is an ASIC prototyping system, therefore we *need* clock gating and want to test this functionality. 

Ash_R_Intel
Employee
361 Views

Hi,

Found this Note in the Intel Quartus Prime Pro Edition User Guide: Design Compilation

https://www.intel.com/content/www/us/en/programmable/documentation/zpr1513988353912.html#oji15700309...


Note: Automatic gated clock conversion supports explicit RAMs (such as WYSIWYG RAMs and Intel FPGA memory IP), but does not support inferred RAMs."


This explains why clock gating did not work for the new RAM component in your design.


Regards


Alexander_Kobler
325 Views

Hi,

Automatic clock gate conversion works when using a memory block generated by Quartus / qmegwiz, so far so fine.

But why does it work for the attached RAM model 256x39, but not for the 64x13?

 

Regards

Ash_R_Intel
Employee
306 Views

Hi,

The tool might be placing the low density memory in the LAB elements instead of the RAM blocks.


Regards.


Alexander_Kobler
294 Views

Hi,

Is it possible to prohibit the tool from using LAB memory, at least for certain instances?

 

Regards

Ash_R_Intel
Employee
279 Views
Alexander_Kobler
270 Views

Hi,

 

Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)

 

But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC

Instead of:

 

  wire s_wen;
  assign s_wen = (~CEN) ? WEN : 1'b1;

 

Changed to:

 

wire [1:0] s_wen;
assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};

 

 

See also attached files.

 

Regards

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