Generate programmable file for MAX-V CPLD using Quartus Prime Lite

[Altera_Forum]

Hi, 

 I have created the hardware design and would now like to generate a programmable file that will be flashed to my MAX-V CPLD. However, just compiling the design in Quartus does not seem to generate any file. Are there any specific steps needed to do in order to generate the file? Also what file extension is it on the file that will be flashed to the CPLD? Thanks.

[Altera_Forum]

Okay, so I can see that a .sof file is generated. Is that enough for the MAX-V or do I also need a .pof? This is a bit unique from Xilinx, can anyone explain why there are different programming file formats?

[Altera_Forum]

You need a Programmer Object File (.pof) to program a MAX V part. SRAM Object Files (.sof) are for direct programming of volatile FPGAs. 

 Quartus Prime Lite should generate this by default. If it's not you need to scan the error/warning messages in Quartus as to why it hasn't generated it. Make sure you search your entire project folder structure for a .pof file in case it's not put it where you expect.  Cheers, Alex

[Altera_Forum]

Hi Alex, 

 Thanks for the reply. I found a .pof file in one of the folders. So this file is enough to flash the MAX-V, right? Also, how can I flash the MAX-V using JTAG? I can see from the pin planner that the JTAG configuration are automatically set to: pin 14 (TMS), pin 15 (TDI), pin 16 (TCK), pin 17 (TDO). How can I proceed to flash to the CPLD using JTAG? Thanks again.

[Altera_Forum]

Yes, that file's all you need. Use the Quartus Programmer (comes as standard with Quartus) with a USB-Blaster (or similar). This will allow you to program the device via JTAG. 

 Cheers, Alex

[Altera_Forum]

Note: you can use a .sof to program a MAX 10 device over JTAG. It just won't get stored in the flash memory.