Generated simulation model for intel_agilex_hps do not provide implementation for f2h_ace interface

[Albert_Waissman]

Hello,

I found that generated simulation mode by design platform for HPS do not provide implementation for this interface.

This interface get passed all the way to:

my_hps.intel_agilex_hps_0.intel_agilex_hps_0.fpga_interfaces

In this module it not connected to any thing.

I can't find any configuration that i may miss.

Any suggestinos?

Thanks,

[sstrell]

Is this your issue? https://www.intel.com/content/www/us/en/support/programmable/articles/000091475.html

[awaissman]

Not sure if this is the issue even seems so.

As i mention ace interface from top gets to fpga_interfaces module and there it's not connected to any where.

Beside this i did not saw any Error for missing interconnect as it mentioned in this issue.

I am going to look for the error first.

Thanks for following up.

[awaissman]

Let me add file where f2h interface terminates.

I changed extention from sv to v to allow upload this file.

[JingyangTeh_Altera]

Hi

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible. 

Thank you for your understanding.

Back to your issue, have you take a look at the simulation flow for the Agilex device in the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683581/22-4/simulation-flows-stratix-10-agilex.html

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Do you have any follow up question on HPS Simulation?

Regards

Jingyang, Teh

[awaissman]

Hi,

Unfortunately i still not able to see simulation.

When i try run simulation from:

agilex5_hps_f2h_simulation/agilex5_hps_f2h_simulation/sim/mentor

I am getting following error:

# ** FATAL: Questa VIP version mismatch detected.
# ** There is a mismatch between the SystemVerilog (version = 20220701) and the BFM (version = 20240212).
# ** Please check your compilation and simulation commands to ensure a consistent QVIP version is in use.

I see this type of error first time.

Questa version 2023.4_3

Quartus version 24.2

Thanks,

[JingyangTeh_Altera]

Hi

Are you using the Agilex5 device?

If so you could take a look at the link below:

https://www.intel.com/content/www/us/en/docs/programmable/786901/24-1/virtual-platforms.html

Regards

Jingyang, Teh

[awaissman]

Hello,

No we are using Agilex7 device.

Thanks,

[JingyangTeh_Altera]

Hi

Are you trying out the simulation flow int he link below:

https://www.intel.com/content/www/us/en/docs/programmable/683581/22-4/running-the-simulations-stratix-10-agilex.html

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh