Re: Generating ALTPLL with the Command Line

Altera_Forum · ‎12-05-2015

I'd like to generate an ALTPLL block (see zip attachment) by means of a command-line tool. I'd like to say something along the lines of:

"C:\altera\15.0\quartus\sopc_builder\bin\ip-generate" --output-directory="." --file-set=QUARTUS_SYNTH --language=VERILOG --component-name=altpll --output-name="PLL" --system-info=DEVICE_FAMILY="MAX 10" --component-parameter=OPERATION_MODE=NO_COMPENSATION --component-parameter=INCLK0_INPUT_FREQUENCY="50 MHz" --component-parameter=CLK0_OUTPUT_FREQUENCY="10 MHz"

This does not work: it ignores the output frequency parameter and generates a complicated .v file (with read and write ports, etc.) instead of the simple .qip and .v (with only "inclk", "c0" and "locked" ports) that the qsys wizard generates (see zip attachment).

Please could someone point me in the direction of a decent manual / examples of how to do this correctly? If possible, I would prefer using the GUI-level parameters, not the low-level parameters, as I want to use a version that is as device-independent as possible.

Altera_Forum · ‎12-13-2015

I found a solution:

C:\altera\15.0\quartus\bin64\qmegawiz -silent ^

module=altpll ^

INTENDED_DEVICE_FAMILY="MAX 10" ^

areset=unused ^

locked=used ^

clk0=used ^

OPERATION_MODE=NO_COMPENSATION ^

INCLK0_INPUT_FREQUENCY=20000 ^

CLK0_DIVIDE_BY=5 ^

PLL.v

The CLK0_OUTPUT_FREQUENCY still doesn't work, and it ignores the "areset=unused" line, but I can work around that...

Altera_Forum · ‎12-17-2015

Thanks for sharing your solution.

Altera_Forum · ‎12-17-2015

I found an even better solution: Quartus models the PLL and RAM megafunctions (IP blocks) as parametrised HDL modules, so you can instantiate it directly. I'm auto-generating (for example) the Verilog code:

// For the MAX 10 (and Cyclone IV and below):
altpll# (
 .operation_mode("NO_COMPENSATION"),
 .inclk0_input_frequency(20000), // 50 MHz
 .clk0_multiply_by(1),
 .clk0_divide_by  (5),
 .clk1_multiply_by( 1),
 .clk1_divide_by  (10),
 .clk2_multiply_by( 1),
 .clk2_divide_by  (20),
 .clk3_multiply_by( 1),
 .clk3_divide_by  (40),
 .clk4_multiply_by( 1),
 .clk4_divide_by  (80),
 .width_clock(5)
)PLL(
 .inclk ({1'b0, Clk}),
 .clk   (Clk_Out),
 .locked(Locked)
);
// For the Cyclone V (and any other higher-end modern FPGA):
altera_pll# (
 .fractional_vco_multiplier("false"),
 .reference_clock_frequency("50 MHz"),
 .operation_mode("direct"),
 .number_of_clocks(5),
 .output_clock_frequency0("10 MHz"),
 .output_clock_frequency1("5 MHz"),
 .output_clock_frequency2("2.5 MHz"),
 .output_clock_frequency3("1.25 MHz"),
 .output_clock_frequency4("0.625 MHz"),
 .pll_type("General"),
 .pll_subtype("General")
)PLL(
 .rst   (Reset),
 .outclk(Clk_Out),
 .locked(Locked),
 .refclk(Clk)
);

Altera_Forum · ‎12-17-2015

this solution looks longer in term of code size.

Altera_Forum · ‎12-17-2015

It's because it's a more elaborate example. The equivalent of the batch file I posted earlier is:


altpll# (
 .operation_mode("NO_COMPENSATION"),
 .inclk0_input_frequency(20000), // 50 MHz
 .clk0_multiply_by(1),
 .clk0_divide_by  (5),
 .width_clock(5)
)PLL(
 .inclk ({1'b0, Clk}),
 .clk   (Clk_Out),
 .locked(Locked)
);

More importantly though: this is the only code you need. You don't need to have more HDL code to instantiate the mega-wizard generated module, as you would in my original solution.

Altera_Forum · ‎12-17-2015

The way I usually do it is generating the core from Qsys GUI. Then go to its log window, and copy the entire command +parameters.

High-level command in Quartus 15.x is qsys-generate.

The command looks something like this (just copying from my script):

$ALTERA_PATH/sopc_builder/bin/qsys-generate

$qsys_name

--synthesis=VERILOG

--output-directory="$qsys_dir"

--family="$fpga_family"

--part="$fpga_part" 2>&1 | tee -a $LOGFILE

Altera_Forum · ‎12-17-2015

I'll definitely keep this in mind for automating the more complex IP blocks - thank you :-)