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15308 Discussions

Get warnings when constraining Clock and Generated clocks


am trying to build the following.clock circuits. Although it works, I am not able to get the constraints to work:

Basically I have a 20 MHz input clock. This generates an 80 MHz clock which in turn is used to generate a 320MHz. The 80 MHz clock is used elsewhere in the design. There are other clocks derived, but I basically I hope that if I can get theese two to work, I can figure out the others.

clock : clock_src
port map(locked => reset_n,
outclk_0 => clk_80mhz,
outclk_1 => clk_75mhz,
outclk_2 => clk_80mhz_shift,
refclk => FPGA_MASTER_CLK,
rst => L0);
h_pll : highlands_pll
port map (locked => open,
outclk_0 => clk320_mhz,
outclk_1 => clk25_6mhz,
refclk => clk_80mhz,
rst => reset);

Both pll's are Integer mode
I set the following constraints :

create_clock -name {FPGA_MASTER_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {FPGA_MASTER_CLK}]

create_generated_clock -name {clk_80mhz} -source [get_ports {FPGA_MASTER_CLK}] -multiply_by 4 -master_clock {FPGA_MASTER_CLK} [get_pins {clock|clock_src_inst|altera_pll_i|outclk_wire[0]~CLKENA0|outclk}]
create_generated_clock -name {clk320_mhz} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -multiply_by 4 -master_clock {clk_80mhz} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|outclk_wire[0]~CLKENA0|outclk}]

When I compile I get the following message:
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000
Warning (332056): Node: h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 12.500

What am I doing wrong?

I am using Quartus standard for cyclone V

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4 Replies
Honored Contributor III

The warnings seem to indicate that the targets of your create_generated_clock commands are incorrect.  Did you use the Name Finder (accessed from the timing constraint GUI dialog boxes) to search for the correct targets for get_pins?

The easiest thing to do would be to simply remove the create_generated_clock constraints and use derive_pll_clocks.



The warning is on the PLL's internal VCO, which we don't constraint. There is no impact on the output clock.

Best is to apply use following two constraints:

1) create_clock -name {FPGA_MASTER_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {FPGA_MASTER_CLK}]

2) derive_pll_clocks

The constraint derive_pll_clocks automatically derives the PLL output clocks based on the settings made in the IP. This helps user to get rid of the create_generated_clock constraints on the PLL outputs.

After applying derive_pll_clocks constraint, check the Fitter report. You will find below info:

Info (332111): Found 8 clocks

Info (332111):  Period  Clock Name

Info (332111): ======== ============

Info (332111):  0.833 clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]

Info (332111):  12.500 clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

Info (332111):  13.333 clock|clock_src_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk

Info (332111):  12.500 clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk

Info (332111):  50.000 FPGA_MASTER_CLK

Info (332111):  1.562 h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]

Info (332111):  3.125 h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

Info (332111):  39.062 h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk

Note in the above, the tool automatically identified the clocks which it was complaining about.

More details on derive_pll_clocks can be found in Intel Quartus Prime Standard Edition User Guide: Timing Analyzer



I used the GUI to create the clocks. So yes, I did use the name finder.

I used use derive_pll_clocks and got the following:

create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 32 -divide_by 2 -master_clock {FPGA_MASTER_CLK} [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -phase 90/1 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 25 -master_clock {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]

The clocks output by clock_src are:
outclk_0 = clk_80mhz 
outclk_1 = clk_75mhz
outclk_2 = clk_80mhz_shift
of which clk_80mhz is used as both a clock and the reference clock for highlands_pll
clk_75mhz is not connected to anything in this design
clk_80mhz_shift is a 90 degree shift of clk_80mhz which is not 8used as a clock in the FPGA but is output to clock other ICs.

The clocks outputs of highlands_pll are:
outclk_0 = clk320_mhz
outclk_1 = clk25_6mhz
where both clk320_mhz and clk25_6mhz are used as clock  in the FPGA

how do these clock names correspond to  names in the derived clocks?


Map them this way:

clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]  --> Internal VCO of clock_src 

clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_0 of clock_src

clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_2 of clock_src

h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]  --> Internal VCO of highlands_pll

h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_0 of highlands_pll

h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_1 of highlands_pll

Now substitute in constraint:

create_generated_clock -name {Internal VCO of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 32 -divide_by 2 -master_clock {FPGA_MASTER_CLK} [get_pins {Internal VCO of clock_src}]

This is (20*32)/2 = 320 MHz (internal)

create_generated_clock -name {outclk_0 of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {Internal VCO of clock_src} [get_pins {outclk_0 of clock_src}]

This is (320*1)/4 = 80 MHz

create_generated_clock -name {outclk_2 of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -phase 90/1 -master_clock {Internal VCO of clock_src} [get_pins {outclk_2 of clock_src}]

This is (320*1)/4 = 80 MHz with 90 degree phase shift

create_generated_clock -name {Internal VCO of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {outclk_0 of clock_src} [get_pins {Internal VCO of highlands_pll}]

This is (80*16)/2 = 640 MHz (internal)

create_generated_clock -name {outclk_0 of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {Internal VCO of highlands_pll} [get_pins {outclk_0 of highlands_pll}]

This is (640*1)/2 = 320 MHz

create_generated_clock -name {outclk_1 of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 25 -master_clock {Internal VCO of highlands_pll} [get_pins {outclk_1 of highlands_pll}]

This is (640*1)/25 = 25.6 MHz