Getting Signal Tap to discover the last time a trigger condition happens

[Altera_Forum]

Hi, 

 I'm debugging a communication Interface between my FPGA Design and an external Microcontroller. It should transfer about 1000 packets of data via SPI, but always fails during the transfer. Sometimes it fails after transferring 10 Packets, sometimes it fails after transferring 50 packets. It always seems to miss a change of the chip select input signal, comming from the Microcontroller, so I tried to set the trigger Condition to "falling edge" for the chip select signal. Now when I start signal tap with the Autorun Analysis Button, it triggers the first falling edge of the chip select signal and stops then. But what I expect signal tap to do is recapturing my signals every time chip select has a falling edge, so that it stops at the last time the signal changed and I'm able to see all signal states at that moment. If I run Signal Tap with only don't care trigger conditions, I'm able to see where the packet counter stopped, so I'm sure that chip select went low several times after the first event captured. So what is the problem here and how do I configure Signal tap to behave the way I want it to?

[Altera_Forum]

--- Quote Start ---  Hi,  I'm debugging a communication Interface between my FPGA Design and an external Microcontroller. It should transfer about 1000 packets of data via SPI, but always fails during the transfer. Sometimes it fails after transferring 10 Packets, sometimes it fails after transferring 50 packets. It always seems to miss a change of the chip select input signal, comming from the Microcontroller, so I tried to set the trigger Condition to "falling edge" for the chip select signal. Now when I start signal tap with the Autorun Analysis Button, it triggers the first falling edge of the chip select signal and stops then. But what I expect signal tap to do is recapturing my signals every time chip select has a falling edge, so that it stops at the last time the signal changed and I'm able to see all signal states at that moment. If I run Signal Tap with only don't care trigger conditions, I'm able to see where the packet counter stopped, so I'm sure that chip select went low several times after the first event captured. So what is the problem here and how do I configure Signal tap to behave the way I want it to?  --- Quote End ---    check your timing and clocking as well as signaltap clock that samples the chip select. Ideally I will use same clock(or faster) in signaltap as the one on the register I monitor.

[Altera_Forum]

I use the same clock (50MHz) for Signal Tap, that clocks the SPI Logic in my FPGA design. 

For me, it seems as if the error always happens while the on chip Signal Tap logic offloads it's data to the computer. Sometimes it captures 2 or 3 events, e.g. the first transfer, then the 25th transfer and so on, but nothing between because Signal Tap is busy offloading it's data in between. So is there any option, that the on chip logic always stores data when the trigger condition happens but waits until I tell it to transfer the data to the computer? This could make it possible to just watch the data at the last moment the trigger condition happened.

[Altera_Forum]

--- Quote Start ---  I use the same clock (50MHz) for Signal Tap, that clocks the SPI Logic in my FPGA design. For me, it seems as if the error always happens while the on chip Signal Tap logic offloads it's data to the computer. Sometimes it captures 2 or 3 events, e.g. the first transfer, then the 25th transfer and so on, but nothing between because Signal Tap is busy offloading it's data in between. So is there any option, that the on chip logic always stores data when the trigger condition happens but waits until I tell it to transfer the data to the computer? This could make it possible to just watch the data at the last moment the trigger condition happened.  --- Quote End ---    Did you ever solve this?   I am running into the same issue.

[Altera_Forum]

Set the trigger position to pre-trigger and then set up the sample qualification to capture what you want to see after the trigger condition occurs. This will cause the samples you don't care about after the trigger to not be stored in the buffer. The sample discontinuities will be marked if you enable that option.

[Altera_Forum]

--- Quote Start ---  Set the trigger position to pre-trigger and then set up the sample qualification to capture what you want to see after the trigger condition occurs. This will cause the samples you don't care about after the trigger to not be stored in the buffer. The sample discontinuities will be marked if you enable that option.  --- Quote End ---    What do you mean by "set up the sample qualification"?