Getting 'Timing requirements not met' as critical warning

[Altera_Forum]

Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing requirements not met. It seems like it is complaining about the following component where the external clock is divided into a lower clock frequency that is used by the other components in the design: 

 entity clk_divider is generic (COUNTER_MAX : integer := 256000); port( clk_in : in std_logic; reset : in std_logic; clk_out : out std_logic ); end clk_divider; --------------------------------------------------- architecture Behavioral of clk_divider is signal signal_level : std_logic := '0'; signal counter : integer range 0 to COUNTER_MAX := 0; begin clk_divider : process (clk_in, reset) begin if (reset = '1') then signal_level <= '0'; counter <= 0; elsif rising_edge(clk_in) then if (counter = COUNTER_MAX) then signal_level <= not(signal_level); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk_out <= signal_level; end Behavioral;  The critical warning message shown during design compilation is shown below:  Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name clk clk Info (332105): create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -7.891 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -7.891 -123.541 clk Info (332119): -1.602 -5.110 clk_divider:clk_module|signal_level Info (332146): Worst-case hold slack is -0.816 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.816 -0.816 clk Info (332119): 1.732 0.000 clk_divider:clk_module|signal_level Info (332146): Worst-case recovery slack is -4.190 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -4.190 -20.950 clk_divider:clk_module|signal_level Info (332119): -3.654 -76.734 clk Info (332146): Worst-case removal slack is 4.320 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.320 0.000 clk Info (332119): 4.856 0.000 clk_divider:clk_module|signal_level Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.289 -2.289 clk Info (332119): 0.247 0.000 clk_divider:clk_module|signal_level Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements  What is the reason for this warning message and how can I solve it? Also what does the slack numbers say about my design?  Thanks.

[Altera_Forum]

Have you created your own timing constraints? if you dont, it will try and make it meet a 1GHz clock, which will never meet timing. 

You need to provide your own timing constraints.

[Altera_Forum]

Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

 That's your first problem. You should add an SDC file which at the very least contains a "create_clock" for any clock input, and the commands "derive_pll_clocks -create_base_clocks" (if you have any PLLs) and "derive_clock_uncertainty".  The constraints file tells TimeQuest and Quartus what frequency your clock signals run at so it knows how to optimise and can give you an idea of the whether your design will run correctly without timing issues caused by propagation delays, etc.  Without a constraints file, Quartus assumes all clocks in the design run at 1GHz ("Calling derive_clocks -period 1.0") at which point pretty much every design would fail timing.   Setup slack means the amount of time that a clock signal reached a register in your design *before* the data would have got there. If a clock reaches a register before the data, then the value clocked in will be out of sync or some unknown transition value. This is called a setup timing violation and is the bane of all FPGA designers as it makes your design do highly unpredictable things. Timing violations are bad! The fact that your worst case slack is -8ns means your design could probably run at 100MHz, but not at 1GHz - I calculated this as dropping the clock frequency to 100MHz would give you an extra +9ns slack compared with 1GHz which would nicely absorb the negative slack (this is just a simplified example of what it means).  An example file would be:   # # Design Timing Constraints Definitions # set_time_format -unit ns -decimal_places 3 # ############################################################################# # Create Input reference clocks create_clock -name {clkin_50} -period 20.000 -waveform { 0.000 10.000 } # ############################################################################# # Now that we have created the custom clocks which will be base clocks, # derive_pll_clock is used to calculate all remaining clocks for PLLs derive_pll_clocks -create_base_clocks derive_clock_uncertainty   Here I create a clock called "clkin_50" (you can name it whatever you like), specify that it is 50MHz (20ns period), specify it is 50% duty cycle (rising edge at 0ns, falling edge at 10ns), and instruct that the port that the clock is located at (e.g. FPGA pin) is called "clkin_50" via the "[get_ports ]" command. The clock name doesn't have to match the port name, but I find it useful to do so.

[Saravana1987]

Hi Sir
When I add the .sdc file with all requirements such as create_clock and clock derivativity I got the same issue timing requirements not met. I got pll with 210MHz , 17ns and another 17ns with 5ns phase difference and the input clock is 50 MHz, will you please guide me in this issue.
Thanks
T.S.Saravana Kumar

[sstrell]

Probably should create a new topic here in the forum and include your .sdc file and what you're seeing in the timing analyzer.  This is a 6 year old thread.

[Altera_Forum]

Thanks for the reply.  

Yes, it seems like the .sdc was missing. I have added the following lines into my .sdc file:  create_clock -period 488.281 -name clk clk create_clock -period 1000000000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level  For clk I have set to 488.281 (2.048 MHz) and signal_level I have set to 1000000000 (1 Hz) since I want to have clk_divider (clk_out output) as 1 Hz clock. However, I get a warning saying that:  Warning (332049): Ignored create_clock at synopsys-design-constraints.sdc(2): Time value "1000000000" is not valid Info (332050): create_clock -period 1000000000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level   What have I done wrong? Thanks

[Altera_Forum]

You shouldn't need to define output clocks. Only inputs. 

 If you do want to define an output clock, that is done using a different command:   # Create a generated clock: -name = name of new clock, -divide_by = output frequency is input divided by this, -source = original clock, then end of line is the target signal where output clock is. create_generated_clock -name clk_divider_out -divide_by 2048000 -source clk clk_divider:clk_module|signal_level

[Altera_Forum]

Thanks. So if I used the top-module clock input to create the inner clk_out, then I only need to create_clock for the top-module clock, right? 

 If I only use create_clock for the top-module clock and not the internal signal, I get the following warning: Warning (332060): Node: clk_divider:clk_module|signal_level was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fsm:fsm|current_state.READ_STATE is being clocked by clk_divider:clk_module|signal_level

[Altera_Forum]

Ah, I see what you are doing. Ideally you shouldn't use clocks generated in logic as actual clocks. Instead the clock divider would generate a 1-fast-clock-cycle pulse every 2048000 clock cycles. You would then use this pulse as an enable signal for your registers which are instead clocked by the fast clock. That way they only get clocked once every 2048000 cycles. 

 Given you are dealing with low frequencies, it shouldn't be such an issue (though you will get a very jittery clock). If you continue with your approach you will need the create_generated_clock command.

[Altera_Forum]

TCWORLD, thanks for the recommendation. I appreciate it. I have modified the code a clock pulse instead of generating a clock in logic and the timing requirement warning has gone.  

 I should probably create a new thread about this, but I will ask it here anyway: Do I need to purchase a Quartus Prime license in order to flash to MAX-V CPLD or can I use the Quartus Lite version? I only need to generate a programmable file and not debugging features etc.

[Altera_Forum]

Hi Sallo, 

 You should not need the license, you can refer to https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/po/ss-quartus-comparison.pdf for the different btw Lite and Std and Pro.  Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation)