Hello,
I'm trying to predict the power consumption of my VHDL design using PowerPlay Analizer in Quartus Prime SE. For that I'm doing the gate level simulation with Modelsim-Altera 10.5b with the option 'generate VCD file' turned on. My problem is that there is no difference in the estimated current consumption of the design when I modify the 'Enable glitch filtering' option under 'EDA Tool settings>Simulation'. Anyone knows what may be the cause for this? Fyi, the 'Perform glitch filtering on VCD files' under 'PowerPlay Power Analizer Settings' does modify the estimated current value.
Edit: I forgot to mention that the design is intended for a Cyclone V device which may be the cause of the issue, since
gate-level timing simulation is no longer supported for this devices. From the 'Quartus Prime SE Handbook vol 3: Verification' document:
"note: gate-level timing simulation of an entire design can be slow and should be avoided. gate-level timing simulation is supported only for the stratix iv and cyclone iv device families. use timequest static timing analysis rather than gate-level timing simulation."
Correct me if I'm wrong, but isn't timing simulation the way to bring up glitches? I have also found another thread that supports this conclusion (see posts# 9 and# 10):
http://www.alteraforum.com/forum/showthread.php?t=36762 Regards,
Federico
