Got problems on running 32*32 multiplier vhdl code running on quartus at linux OS

[Altera_Forum]

HI everyone please help me. my code is library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mult32bit is generic ( DATA_WIDTH : integer := 32 ); port( a : in std_logic_vector(DATA_WIDTH-1 downto 0); e : in std_logic_vector(23 downto 0); --PARAM d : in std_logic_vector(7 downto 0); --PARAM c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0) ); end mult32bit; architecture Behavioral of mult32bit is signal b : std_logic_vector(31 downto 0); signal right : std_logic_vector((DATA_WIDTH)-1 downto 0); signal left : std_logic_vector((DATA_WIDTH)-1 downto 0); signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0); signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0); begin b a(15 downto 0), b => b(15 downto 0), c => right ); MULTIPLIER_left:entity work.mult16bit port map( a => a(31 downto 16), b => b(31 downto 16), c => left ); left_shifted b(15 downto 8), c => left ); left_shifted

[Altera_Forum]

Hi 

Any chance you can repost with carridge returns?

[Altera_Forum]

what do you mean by carridge returns? i do not understand . Please elaborate

[Altera_Forum]

Please re-post the code in a readable state. With some whitespace, like enter key at end of lines, and preferably with code tags.

[Altera_Forum]

32*32 vhdl code is 

 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  library work; use work.all;    ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;  entity mult32bit is generic (  DATA_WIDTH : integer := 32 ); port(  a : in std_logic_vector(DATA_WIDTH-1 downto 0);  e : in std_logic_vector(15 downto 0); --PARAM  d : in std_logic_vector(15 downto 0); --PARAM  c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0)  ); end mult32bit;  architecture Behavioral of mult32bit is    signal b : std_logic_vector(31 downto 0);  signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);  signal left : std_logic_vector((DATA_WIDTH)-1 downto 0);  signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0);  signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0); begin  b <= e & d;  MULTIPLIER_right:entity work.mult16bit  port map(   a => a(15 downto 0),  b => b(15 downto 0),  c => right );   MULTIPLIER_left:entity work.mult16bit  port map(   a => a(31 downto 16),  b => b(31 downto 16),  c => left );     left_shifted <= left & "00000000000000000000000000000000" ;  -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));    new_right <= "00000000000000000000000000000000" & right;      c <= unsigned(new_right) + unsigned(left_shifted) ;    end Behavioral;    mult16bit code is  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  library work; use work.all;    ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;  entity mult16bit is generic (  DATA_WIDTH : integer := 16 ); port(  a : in std_logic_vector(DATA_WIDTH-1 downto 0);  e : in std_logic_vector(7 downto 0); --PARAM  d : in std_logic_vector(7 downto 0);  --PARAM  c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0)  ); end mult16bit;  architecture Behavioral of mult16bit is   signal b : std_logic_vector(15 downto 0);  signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);  signal left : std_logic_vector((DATA_WIDTH)-1 downto 0);  signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0);  signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0); begin  b <= d & e;  MULTIPLIER_right:entity work.mult8bit  port map(   a => a(7 downto 0),  b => b(7 downto 0),  c => right );   MULTIPLIER_left:entity work.mult8bit  port map(   a => a(15 downto 8),  b => b(15 downto 8),  c => left );     left_shifted <= left & "0000000000000000" ;  -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));    new_right <= "0000000000000000" & right;      c <= unsigned(new_right) + unsigned(left_shifted) ;    end Behavioral;  my errors are  Error (10349): VHDL Association List error at mult32bit.vhd(42): formal "b" does not exist mult32bit.vhd Line: 42  Error (10346): VHDL error at mult32bit.vhd(38): formal port or parameter "e" must have actual or default value mult32bit.vhd Line: 38  Error (10784): HDL error at mult16bit.vhd(21): see declaration for object "e" mult16bit.vhd Line: 21  Error (10346): VHDL error at mult32bit.vhd(38): formal port or parameter "d" must have actual or default value mult32bit.vhd Line: 38  Error (10784): HDL error at mult16bit.vhd(23): see declaration for object "d" mult16bit.vhd Line: 23

[Altera_Forum]

mult16bit code is working but 32*32 is not working .please help me

[Altera_Forum]

the mult16 entity has no b port, so you cannot connect an item to it as it does not exist. 

Also, it has an "e" port that is an input so must be connected to something. The same goes for the "d" port on the mult8bit entity.

[Altera_Forum]

Can you help me how can i correct these errors. please

[Altera_Forum]

For the B port - connect the data to an existing port. 

for "e" and "d" port errors - connect something to them.

[Altera_Forum]

please can u do that in the code and send me i am very thankful to you. i have dead line today so please help me

[Altera_Forum]

I will not do your work for you. 

You need to work out what needs to be connected and correct the code. I dont know what you want to connect to those ports.

[Altera_Forum]

Ok thank you very much for your kind help.you r very kind. Thanks

[Altera_Forum]

can you please tell what is the existing port.