HPS CLK Initialization issue

[Veerappan]

Hi team,

              In our custom board, we use AGFB014R24B1E1V Intel SoC FPGA. When HPS runs FSBL, the HPS CLK does not get initialized. It is stuck waiting for the main and peripheral PLL lock, but the hardware side clock is fine. Please help resolve the problem and give a procedure to configure HPS CLK in Quartus Prime.

Thanks,

Regards,

Veerappan P.

[Veerappan]

Hi,

   I have doubts about the CLK manager status register main pll lock bit. The issue is the mainplllocked bit is not set. The doubt is where the PPM threshold value is programmed in the memory register. 

 

Thanks,

Regards,

Veerappan P.

[khtan]

Hi Veerappan,

Sorry for the delay in getting back to you as I was out on emergency last week. Let me check this up and get back to you later.

Thanks

Regards

Kian

[khtan]

Hi Veerappan,

Just to confirm

In platform designer , the EOSC clock frequency used is the correct frequency and the settings for both input and output clocks are set accordingly

example cyclone V (for agilex you should have 1 EOSC clock only)

then since you're running on custom board, have you regenerated the spl and also check the bootloader osc clock settings are set correctly?

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/arch/arm/dts/socfpga_agilex_socdk.dts (do change the file depending on which board you're referencing to. I'm using agilex soc dev kit)

May I know where do you find this table from , at which document. Was trying to find this on my end

Thanks

Regards

Kian

[Veerappan]

Hi,

You say 

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/arch/arm/dts/socfpga_agilex_socdk.dts (do change the file depending on which board you're referencing to. I'm using agilex soc dev kit)

What changes are made in that file?

soc {
             clocks {
                           osc1 {
                                         clock-frequency = <25000000>;
                            };
               };
};

This clock device tree parameter is enough to add the clock or some other properties are required. We followed the Apollo Agilex 7 SOM board design for our custom board.

This image is taken from the i_clk_mgr_clkmgr register map. The Register Address is 0xFFD10000.

 

Thanks,

Regards,

Veerappan P.

[Veerappan]

Hi,

 I have gone through the U-boot clock initialization C code but there is no device tree parameter given in .dts file used for clock initialization. 

u-boot-socfpga/drivers/clk/altera/clk-agilex.c In this file this is the probe function

static int socfpga_clk_probe(struct udevice *dev)
{
struct cm_config *cm_default_cfg = cm_get_default_config();
clk_basic_init(dev, cm_default_cfg);
return 0;
}

cm_get_default_config();  function is used to get clock configuration information from FPGA and if we go through the clk_basic_init(); function. This data which is from FPGA hands-off is used. Then why do we use clock parameters in the device tree?

Thanks,

Regards,

Veerappan P.

[khtan]

Hi Veerappan,

Apologies for the long delay in replying , was on medical leave for 2 weeks and my forum account access got revoked, just manage to regain access this week.

I will look into this case and feedback to you later, once again I'm sorry for the long response delay.

Thanks

Regards

Kian

[khtan]

####

Sorry, I didn't notice my message didnt get through and was stuck in draft state. Just resend out

Thanks

Regards

Kian

####

Hi Veerapan,

Apologies, on your question, this KDB might answer your questions even though it is based on Stratix 10, but it is also applicable for Agilex as well

https://www.intel.com/content/www/us/en/support/programmable/articles/000086394.html

As we are using das u-boot and  linux kernel , more information can be obtain from their respective sites

https://docs.kernel.org/devicetree/index.html#devicetree-overlays

https://docs.u-boot.org/en/latest/build/index.html

Thanks

Regards

Kian

[khtan]

Hi,

May I know whether you have further question related to the case , otherwise I would like to transition the case to community support.

Thanks

Regards

Kian

[khtan]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Once again I do apologize for the delay in getting back. I will try to address the discussion at the other thread

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-use-HPS-internal-clock-in-Agilex-7-SOC/m-p/1658943#M29125

Thanks

Regards

Kian