Hello, I would like to know how do I code fixed point arithmetics (add/sub/divide/multiply/abs/round) for cyclone V FPGA device. I am coding VHDL on Quartus prime standard edition version 18.1

[JOHI]

Hello DKras4

Your question is very broad.

It would be easier to help you if your question was more specific.

What kind of project are you working on?

There is a manual at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fxp_mf.pdf for fixed point arithmatic with a lot of ip . However the standard IEEE vhdl libaries can also get you where you want depending on Your needs.

Best Regards,

Johi.

[DKras4]

Hello,

In the fixed point user manual at the section "About IP cores" I can see that the target device is Arria 10 only and support only by PRO version of Quartus.

My target device is CYCLONE 5 and I am using Prime Standard version.

To be more specific :

1)Where I can find the Fix Point IPs in the IP catalog or Qsys of the Prime Standard edition?

2)Lets say I want to write function by myself that implement add/mult of the fix point numbers.

How can I do it?

Where I can get package that supports FIX point signed/unsigned numbers?

Thanks

[JOHI]

Hello DKras4

IP blocks for calculations can be found as indicated above.

Included one of my test projects I am working on, it does calculations in floating point and fixed point with ip blocks (and a natural logarithm ln()). You might get some inspiration out of it. All is targeted Cyclone V DE10_STANDARD.

If you want to do only simple fixed point calculations, you can code it directly in VHDL, no need for IP blocks.

Below a timer component that effectively counts clock pulses to wait for a certain period of time.

The objective of the block is to extend the signal "Ein" for a certain period of time.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;entity ent_sa_timer is generic( clk_f : in real:=50.0E6; t : in time:=1sec); port( clk : in std_logic; reset_p: in std_logic:='0'; ein : in std_logic; aus : out std_logic); end entity;     architecture arch_sa_timer of ent_sa_timer is   signal ctr : integer:=0; signal T_Clock : time:=1.0/clk_f*1sec; signal ein_local : std_logic;   begin process (clk, reset_p) begin if rising_edge(clk) then if ein_local='1' then ctr<=ctr; elsif ctr>0 then ctr<=ctr-1; end if; ein_local<=ein; end if; end process; aus<='1' when ctr>0 else '0'; end architecture;

The line ctr<=ctr-1 decreases the value of ctr with 1 each time there is a rising_edge of clk.

You can do all kinds of mathematical functions with it mod * + / etc. and you can combine other variables as well.

No need to parametrize Ip blocks for these simple functions.

Best Regards,

Johi.