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Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this:
An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance!Link Copied
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--- Quote Start --- Hi guys, in my current setting i'm using a streaming mode FFT but thats just because it was the default setting. Another mode can help me get rid of serieus M4K-block issues. The system I have setup is like this: An external ADC is hooked on my Altera DE-1 board. The serial output of this ADC is put in a 12-bit bus and than stacked in a FIFO of 2048 words. When the FIFO is full, the FFT is activated and get's the 2048 samples. When this is done the ADC is activated again. Should I maybe use the burst, buffered burst mode of the FFT or just stick with streaming? Thanks in advance! --- Quote End --- I am no expert on current altera fft (but used it a decade ago ! when it was one mode only and I converted it to streaming mode) . If indeed you can wait stopping the ADC then you can go for burst mode which requires minimum memory. If your ADC bursts are shorter than burst mode then you can go for buffer burst which uses some memory. If on the other hand you must keep ADC running always then you need to use streaming mode in which case you don't need pre-buffering as it is done inside fft using a lot of memory. To give you an idea about streaming that I did: I used two fft cores each running after the other plus memory for two frame buffering. first frame of input data was buffered completely then fft1 started meanwhile second frame was passed to its buffer. Once fft1 was done data was output and fft2 starts processing from its buffer while input passed to 1st buffer and so on. Now all this is done by choosing streaming mode avoiding all that trouble.
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I'm getting very confused in how to use the FFT properly right now. I'm now using burst mode and a single output engine. I do get output from the FFT but when I use pythagoras on it (sqrt(real*real+imaginary*imaginary)) I get very high values. Sometimes with no audio input at all.
My adc puts in a binary number around 127 with silence and goes up to 4096 as full number. Here is my code which is a state machine, which feeds the FFT. Please look at it and let me know what i'm doing wrong.library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity FFTStatemachine is
port( clk,clk32mhz,reset,enable,deserializerdone: IN std_logic;
enabledeserializer,writefifotestled,source_valid: OUT std_logic;
fifoinput : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
fifooutput : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
source_sop : OUT STD_LOGIC;
source_eop :OUT STD_LOGIC
);
end entity;
--------------------------------------
architecture implementation of FFTStatemachine is
component FFT is
port (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
inverse : IN STD_LOGIC;
sink_valid : IN STD_LOGIC;
sink_sop : IN STD_LOGIC;
sink_eop : IN STD_LOGIC;
sink_real : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
sink_imag : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
source_ready : IN STD_LOGIC;
sink_ready : OUT STD_LOGIC;
source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
source_sop : OUT STD_LOGIC;
source_eop : OUT STD_LOGIC;
source_valid : OUT STD_LOGIC;
source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
source_real : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
source_imag : OUT STD_LOGIC_VECTOR (13 DOWNTO 0)
);
end component;
component FIFO is
port (
rdclk : IN STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdfull : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
rdreq : IN STD_LOGIC
);
end component;
-- Signals & Variables --
-------------------------------------------------------------------
-- state definitions and signals ----------------------------------
-------------------------------------------------------------------
type state is (
Idle,
WriteFIFO,
FIFOLatency,
Startreading,
ReadFIFO,
Finishreading,
Finished
);
signal present_state, next_state: state;
signal enablefifolatencycounter: std_logic;
signal enablefifosamplecounter: std_logic;
signal FIFOlatencycounter: integer range 0 to 10:=0;
signal fifocounter : integer range 0 to 3000:=0;
signal done :std_logic;
--FFT local input signals
signal inverse : std_logic :='0';
signal sink_valid : std_logic;
signal sink_sop : std_logic;
signal sink_eop : std_logic;
--signal sink_real : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal sink_imag : STD_LOGIC_VECTOR (13 DOWNTO 0):="00000000000000";
signal sink_error : STD_LOGIC_VECTOR (1 DOWNTO 0) :="00";
signal source_ready : STD_LOGIC;
--FFT local output signals
signal sink_ready : STD_LOGIC;
--signal source_sop : STD_LOGIC;
--signal source_eop : STD_LOGIC;
--signal source_valid : STD_LOGIC;
--FIFO local inputs
signal enablewriting : STD_LOGIC;
signal enablereading : STD_LOGIC;
signal clearfifo : STD_LOGIC;
--FIFO local outputs
signal fifo_out :std_logic_vector (13 downto 0);
signal readempty :std_logic;
signal readfull :std_logic;
signal writeempty :std_logic;
signal writefull :std_logic;
----------------------------------------------------------------------
--PORTMAPS------------------------------------------------------------
----------------------------------------------------------------------
begin
FastFourierTransform: FFT PORT MAP (clk,reset,inverse,sink_valid,sink_sop,sink_eop,fifo_out,sink_imag,sink_error,source_ready,sink_ready,source_error,source_sop,source_eop,source_valid,source_exp,source_real,source_imag);
FIFORAM : FIFO PORT MAP (clk,writeempty,writefull,fifo_out,readempty,readfull,clk32mhz,deserializerdone,clearfifo,fifoinput,enablereading);
------------------------------------------------------------------
-- sequential part of the statemachine ----------------------------
-------------------------------------------------------------------
fifooutput<=fifo_out;
writefifotestled<=sink_ready;
process(reset, clk, next_state)
begin
if (reset = '0') then
clearfifo<='1';
present_state <= Idle;
elsif (rising_edge(clk)) then
clearfifo<='0';
present_state <= next_state;
end if;
end process;
process(present_state,next_state, enable,sink_sop,fifocounter,done,writeempty,writefull,readempty,sink_ready,FIFOlatencycounter)
begin
case present_state is
when Idle =>
if enable ='1' and writeempty = '1' then
next_state <= WriteFIFO;
else
next_state <=Idle;
end if;
when WriteFIFO =>
if writefull ='1' then
next_state <= FIFOlatency;
else
next_state <=WriteFIFO;
end if;
when FIFOlatency =>
if FIFOlatencycounter = 1 then
next_state <= Startreading;
else
next_state <=FIFOlatency;
end if;
when Startreading =>
if sink_sop ='1' then
next_state <= ReadFIFO;
else
next_state <=Startreading;
end if;
when ReadFIFO =>
if fifocounter = 511 then
next_state <= Finishreading;
else
next_state <=ReadFIFO;
end if;
when Finishreading =>
if readempty ='1' then
next_state <= Finished;
else
next_state <= Finishreading;
end if;
when Finished =>
if done = '1' and sink_ready = '1' then
next_state <= Idle;
else
next_state <=Finished;
end if;
end case;
end process;
process(present_state,clk)
begin
case present_state is
when Idle=>
enablefifosamplecounter<='0';
enablefifolatencycounter<='0';
done <='0';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='0';
sink_valid <='0';
sink_eop <='0';
sink_sop <='0';
source_ready<='1';
when WriteFIFO=>
enablefifosamplecounter<='0';
enablefifolatencycounter<='0';
done <='0';
enabledeserializer<='1';
enablewriting <='1';
enablereading <='0';
sink_valid <='0';
sink_eop <='0';
sink_sop <='0';
source_ready<='1';
when FIFOLatency=>
enablefifosamplecounter<='0';
enablefifolatencycounter<='1';
done <='0';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='1';
sink_valid <='0';
sink_eop <='0';
sink_sop <='0';
source_ready<='1';
when Startreading=>
enablefifosamplecounter<='1';
enablefifolatencycounter<='0';
done <='0';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='1';
sink_valid <='1';
sink_eop <='0';
sink_sop <='1';
source_ready<='1';
when ReadFIFO=>
enablefifosamplecounter<='1';
enablefifolatencycounter<='0';
done <='0';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='1';
sink_valid <='1';
sink_eop <='0';
sink_sop <='0';
source_ready<='1';
when Finishreading=>
enablefifosamplecounter<='1';
enablefifolatencycounter<='0';
done <='0';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='1';
sink_valid <='1';
sink_eop <='1';
sink_sop <='0';
source_ready<='1';
when Finished=>
enablefifosamplecounter<='0';
enablefifolatencycounter<='0';
done <='1';
enabledeserializer<='0';
enablewriting <='0';
enablereading <='0';
sink_valid <='0';
sink_eop <='0';
sink_sop <='0';
source_ready<='1';
end case;
end process;
process(clk, enablefifosamplecounter,fifocounter)
begin
if(rising_edge(clk))and enablefifosamplecounter = '1' then
fifocounter <= fifocounter+1;
end if;
if enablefifosamplecounter = '0' then
fifocounter <=0;
end if;
end process;
process(clk,enablefifolatencycounter,FIFOlatencycounter)
begin
if(rising_edge(clk))and enablefifolatencycounter = '1' then
fifolatencycounter<=fifolatencycounter + 1;
end if;
if enablefifolatencycounter= '0' then
fifolatencycounter <=0;
end if;
end process;
end architecture;
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The best way to check fft output is use an independent model e.g. matlab fft:
y = fft(x,points); then round it as per fft core. The altera fft core wants you to use the output exponent to rescale the output for each block. Also check that your adc input is of correct format(2's complement) and that indeed you are inputting the values you think. Check that input frame is exactly entering the fft as required without any extra zeros or duplicate samples across the whole frame...etc.- Mark as New
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I'm not familier with Matlab. Never used it before but I will see if I can get that package. For now I would like to try that exponent output.
As far as I know I get a signed number out of the FFT, right? What should I do with the exponent number in combination with the real and imaginary output. I have read the FFT manual....but I do not really understand. By the way, the ADC gives out a straight binary of 12 bits, but I put 2 zero's in front of it and then put it in a 14 bit wide FFT. This will make it a signed binary.- Mark as New
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Matlab may have free trial version. There is also has a free version called Octave. Or you may find other fft tools around.
Alternatively you can inject one sample in the frame(otherwise set to zeros) and you should get a cosine/sine wave output at a given frequency(depending on sample location within frame). You can also reverse that by inputting a sine wave then you get a nozero sample surrounded by zeros. Scaling is well documented with example coding in the fft use guide. I don't really remember or know the details of the current core. I used to just shift divide my output by number of bits = exponent (as far as I remember). Note this is not a standard approach but done to the convenience of altera engineers, they have used internally a representation somewhere between 2's complement and standard floating point. Scaling of fft in general is not standardised across various tools so keep that in mind.- Mark as New
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for 2's complement inserting two leading zeros implies scaling by 4, nothing else.
Check the adc datasheet about their format. some adcs use offset binary in which case you just need to invert the sign bit to become 2's complement then you add two leading zeros.- Mark as New
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Just correcting my last notes on fft testing.
injecting of one nonzero sample etc above applies to ifft. For fft: inject a sine wave and you get one mirrored line (two samples or more depending on resolution issues). Injecting one nonzero sample implies impulse and so you get frequencies all over(not that halpful). Injecting constant samples without zeros implies dc so you get one line at zero frequency and so on.- Mark as New
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--- Quote Start --- for 2's complement inserting two leading zeros implies scaling by 4, nothing else. Check the adc datasheet about their format. some adcs use offset binary in which case you just need to invert the sign bit to become 2's complement then you add two leading zeros. --- Quote End --- If I got this unsigned binary 100 (which is 4) and I put 2 zero's in front 00100, the number is still 4 right? but it is now signed because the MSB is standard a 0. I know it is wrong when working with negative values, but keep in mind that the ADC only gives positive values. Please correct me if i'm wrong.
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--- Quote Start --- If I got this unsigned binary 100 (which is 4) and I put 2 zero's in front 00100, the number is still 4 right? but it is now signed because the MSB is standard a 0. I know it is wrong when working with negative values, but keep in mind that the ADC only gives positive values. Please correct me if i'm wrong. --- Quote End --- correct. if ADC outputs positive only then it will have +dc.
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Thanks for answering my (noobish) questions Kaz. I'm currently figuring out what to do with that exponent part. For now I have another question: This is what excel makes of my little formula : FFToutputframe * samplefrequency*FFTPOINTS=spectrum output of FFT.
Can you verify if this is correct? And, should I only use the first 256 results? And for last: I do not have 256 spectrums on the screen. Is it ok to, let say add the amplitudes of 390,625 and 481,25 and then divide it by two, to fit in a 300 to 500 hz range on the screen?
0 200000 512 0
1 200000 512 390,625
2 200000 512 781,25
3 200000 512 1171,875
4 200000 512 1562,5
5 200000 512 1953,125
6 200000 512 2343,75
7 200000 512 2734,375
8 200000 512 3125
9 200000 512 3515,625
10 200000 512 3906,25
11 200000 512 4296,875
12 200000 512 4687,5
13 200000 512 5078,125
14 200000 512 5468,75
15 200000 512 5859,375
16 200000 512 6250
17 200000 512 6640,625
18 200000 512 7031,25
19 200000 512 7421,875
20 200000 512 7812,5
21 200000 512 8203,125
22 200000 512 8593,75
23 200000 512 8984,375
24 200000 512 9375
25 200000 512 9765,625
26 200000 512 10156,25
27 200000 512 10546,875
28 200000 512 10937,5
29 200000 512 11328,125
30 200000 512 11718,75
31 200000 512 12109,375
32 200000 512 12500
33 200000 512 12890,625
34 200000 512 13281,25
35 200000 512 13671,875
36 200000 512 14062,5
37 200000 512 14453,125
38 200000 512 14843,75
39 200000 512 15234,375
40 200000 512 15625
41 200000 512 16015,625
42 200000 512 16406,25
43 200000 512 16796,875
44 200000 512 17187,5
45 200000 512 17578,125
46 200000 512 17968,75
47 200000 512 18359,375
48 200000 512 18750
49 200000 512 19140,625
50 200000 512 19531,25
51 200000 512 19921,875
52 200000 512 20312,5
53 200000 512 20703,125
54 200000 512 21093,75
55 200000 512 21484,375
56 200000 512 21875
57 200000 512 22265,625
58 200000 512 22656,25
59 200000 512 23046,875
60 200000 512 23437,5
61 200000 512 23828,125
62 200000 512 24218,75
63 200000 512 24609,375
64 200000 512 25000
65 200000 512 25390,625
66 200000 512 25781,25
67 200000 512 26171,875
68 200000 512 26562,5
69 200000 512 26953,125
70 200000 512 27343,75
71 200000 512 27734,375
72 200000 512 28125
73 200000 512 28515,625
74 200000 512 28906,25
75 200000 512 29296,875
76 200000 512 29687,5
77 200000 512 30078,125
78 200000 512 30468,75
79 200000 512 30859,375
80 200000 512 31250
81 200000 512 31640,625
82 200000 512 32031,25
83 200000 512 32421,875
84 200000 512 32812,5
85 200000 512 33203,125
86 200000 512 33593,75
87 200000 512 33984,375
88 200000 512 34375
89 200000 512 34765,625
90 200000 512 35156,25
91 200000 512 35546,875
92 200000 512 35937,5
93 200000 512 36328,125
94 200000 512 36718,75
95 200000 512 37109,375
96 200000 512 37500
97 200000 512 37890,625
98 200000 512 38281,25
99 200000 512 38671,875
100 200000 512 39062,5
101 200000 512 39453,125
102 200000 512 39843,75
103 200000 512 40234,375
104 200000 512 40625
105 200000 512 41015,625
106 200000 512 41406,25
107 200000 512 41796,875
108 200000 512 42187,5
109 200000 512 42578,125
110 200000 512 42968,75
111 200000 512 43359,375
112 200000 512 43750
113 200000 512 44140,625
114 200000 512 44531,25
115 200000 512 44921,875
116 200000 512 45312,5
117 200000 512 45703,125
118 200000 512 46093,75
119 200000 512 46484,375
120 200000 512 46875
121 200000 512 47265,625
122 200000 512 47656,25
123 200000 512 48046,875
124 200000 512 48437,5
125 200000 512 48828,125
126 200000 512 49218,75
127 200000 512 49609,375
128 200000 512 50000
129 200000 512 50390,625
130 200000 512 50781,25
131 200000 512 51171,875
132 200000 512 51562,5
133 200000 512 51953,125
134 200000 512 52343,75
135 200000 512 52734,375
136 200000 512 53125
137 200000 512 53515,625
138 200000 512 53906,25
139 200000 512 54296,875
140 200000 512 54687,5
141 200000 512 55078,125
142 200000 512 55468,75
143 200000 512 55859,375
144 200000 512 56250
145 200000 512 56640,625
146 200000 512 57031,25
147 200000 512 57421,875
148 200000 512 57812,5
149 200000 512 58203,125
150 200000 512 58593,75
151 200000 512 58984,375
152 200000 512 59375
153 200000 512 59765,625
154 200000 512 60156,25
155 200000 512 60546,875
156 200000 512 60937,5
157 200000 512 61328,125
158 200000 512 61718,75
159 200000 512 62109,375
160 200000 512 62500
161 200000 512 62890,625
162 200000 512 63281,25
163 200000 512 63671,875
164 200000 512 64062,5
165 200000 512 64453,125
166 200000 512 64843,75
167 200000 512 65234,375
168 200000 512 65625
169 200000 512 66015,625
170 200000 512 66406,25
171 200000 512 66796,875
172 200000 512 67187,5
173 200000 512 67578,125
174 200000 512 67968,75
175 200000 512 68359,375
176 200000 512 68750
177 200000 512 69140,625
178 200000 512 69531,25
179 200000 512 69921,875
180 200000 512 70312,5
181 200000 512 70703,125
182 200000 512 71093,75
183 200000 512 71484,375
184 200000 512 71875
185 200000 512 72265,625
186 200000 512 72656,25
187 200000 512 73046,875
188 200000 512 73437,5
189 200000 512 73828,125
190 200000 512 74218,75
191 200000 512 74609,375
192 200000 512 75000
193 200000 512 75390,625
194 200000 512 75781,25
195 200000 512 76171,875
196 200000 512 76562,5
197 200000 512 76953,125
198 200000 512 77343,75
199 200000 512 77734,375
200 200000 512 78125
201 200000 512 78515,625
202 200000 512 78906,25
203 200000 512 79296,875
204 200000 512 79687,5
205 200000 512 80078,125
206 200000 512 80468,75
207 200000 512 80859,375
208 200000 512 81250
209 200000 512 81640,625
210 200000 512 82031,25
211 200000 512 82421,875
212 200000 512 82812,5
213 200000 512 83203,125
214 200000 512 83593,75
215 200000 512 83984,375
216 200000 512 84375
217 200000 512 84765,625
218 200000 512 85156,25
219 200000 512 85546,875
220 200000 512 85937,5
221 200000 512 86328,125
222 200000 512 86718,75
223 200000 512 87109,375
224 200000 512 87500
225 200000 512 87890,625
226 200000 512 88281,25
227 200000 512 88671,875
228 200000 512 89062,5
229 200000 512 89453,125
230 200000 512 89843,75
231 200000 512 90234,375
232 200000 512 90625
233 200000 512 91015,625
234 200000 512 91406,25
235 200000 512 91796,875
236 200000 512 92187,5
237 200000 512 92578,125
238 200000 512 92968,75
239 200000 512 93359,375
240 200000 512 93750
241 200000 512 94140,625
242 200000 512 94531,25
243 200000 512 94921,875
244 200000 512 95312,5
245 200000 512 95703,125
246 200000 512 96093,75
247 200000 512 96484,375
248 200000 512 96875
249 200000 512 97265,625
250 200000 512 97656,25
251 200000 512 98046,875
252 200000 512 98437,5
253 200000 512 98828,125
254 200000 512 99218,75
255 200000 512 99609,375
256 200000 512 100000
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second part:
257 200000 512 100390,625
258 200000 512 100781,25
259 200000 512 101171,875
260 200000 512 101562,5
261 200000 512 101953,125
262 200000 512 102343,75
263 200000 512 102734,375
264 200000 512 103125
265 200000 512 103515,625
266 200000 512 103906,25
267 200000 512 104296,875
268 200000 512 104687,5
269 200000 512 105078,125
270 200000 512 105468,75
271 200000 512 105859,375
272 200000 512 106250
273 200000 512 106640,625
274 200000 512 107031,25
275 200000 512 107421,875
276 200000 512 107812,5
277 200000 512 108203,125
278 200000 512 108593,75
279 200000 512 108984,375
280 200000 512 109375
281 200000 512 109765,625
282 200000 512 110156,25
283 200000 512 110546,875
284 200000 512 110937,5
285 200000 512 111328,125
286 200000 512 111718,75
287 200000 512 112109,375
288 200000 512 112500
289 200000 512 112890,625
290 200000 512 113281,25
291 200000 512 113671,875
292 200000 512 114062,5
293 200000 512 114453,125
294 200000 512 114843,75
295 200000 512 115234,375
296 200000 512 115625
297 200000 512 116015,625
298 200000 512 116406,25
299 200000 512 116796,875
300 200000 512 117187,5
301 200000 512 117578,125
302 200000 512 117968,75
303 200000 512 118359,375
304 200000 512 118750
305 200000 512 119140,625
306 200000 512 119531,25
307 200000 512 119921,875
308 200000 512 120312,5
309 200000 512 120703,125
310 200000 512 121093,75
311 200000 512 121484,375
312 200000 512 121875
313 200000 512 122265,625
314 200000 512 122656,25
315 200000 512 123046,875
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512 200000 512 200000
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I better explain fft output to you than answer your figures which are not clear to me:
N points fft output means N bins covering frequencies of +/- sampling frequency/2, (and usually indexed as 0 ~ N-1) approximately: bins 0~N/2 represent frequency range 0 ~ Fs/2 (Fs = sampling frequency sample/sec) bins N/2+1 ~ N-1 represent frequency range -Fs/2 ~ 0 thus dc is at start and end(wrap up) If your signal is real only then both halves get equal (mirror) thus frequency of spectrum at point n: f(n) = Fs * n/N in Hz and its amplitude or phase is the value of amplitude or phase at n amplitude = sqrt(Re^2 + Im^2) as you know If you require fft results then use some simple vector e.g. constant, tell me your resolution and I will get you the result.- Mark as New
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Thanks for your explain Kaz. That makes things a bit clearer.
I looked closely to the way I feed the FFT and came to the conclusion that my system is correct. I also now know that the output of the FFT is a block floating point and not a signed integer like I treated it. I now have to find a way to do my Pythagoras thing with this floating point. There is a mecacore function wich converts floating points to integers, but this function only works with 32-bit floats. I got a 14 bit mantissa from the FFT and a 5 bit exponent. I will have to look for a solution here.- Mark as New
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I now got this:
I only need to sign extend it, any tips to do that?
mux:PROCESS(fftexp,fftvalid)
-- VARIABLE sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- sel := s1 & s0; -- concatenate s1 and s0
if (fftvalid = '1') then
CASE fftexp IS
WHEN "110011" =>
full_range_real_out(26 downto 13) <= fftreal; --sll 13; -- -13
full_range_imag_out(26 downto 13) <= fftimag; --sll 13; -- -13
WHEN "110100" =>
full_range_real_out(25 downto 12) <= fftreal; --sll 12; -- -12
full_range_imag_out(25 downto 12) <= fftimag;-- sll 12; -- -12
WHEN "110101" =>
full_range_real_out(24 downto 11) <= fftreal;-- sll 11; -- -11
full_range_imag_out(24 downto 11) <= fftimag; --sll 11; -- -11
WHEN "110110" =>
full_range_real_out(23 downto 10) <= fftreal;-- sll 10; -- -10
full_range_imag_out(23 downto 10) <= fftimag;-- sll 10; -- -10
WHEN "110111" =>
full_range_real_out(22 downto 9) <= fftreal; --sll 9; -- -9
full_range_imag_out(22 downto 9) <= fftimag; -- sll 9; -- -9
WHEN "111000" =>
full_range_real_out(21 downto 8) <= fftreal; --sll 8; -- -8
full_range_imag_out(21 downto 8) <= fftimag; --sll 8; -- -8
WHEN "111001" =>
full_range_real_out(20 downto 7) <= fftreal; --sll 7; -- -7
full_range_imag_out (20 downto 7)<= fftimag; --sll 7; -- -7
WHEN "111010" =>
full_range_real_out(19 downto 6) <= fftreal; --sll 6; -- -6
full_range_imag_out (19 downto 6) <= fftimag; --sll 6; -- -6
WHEN "111011" =>
full_range_real_out(18 downto 5) <= fftreal; --sll 5; -- -5
full_range_imag_out(18 downto 5) <= fftimag; --sll 5; -- -5
WHEN "111100" =>
full_range_real_out(17 downto 4) <= fftreal; --sll 4 -- -4
full_range_imag_out(17 downto 4) <= fftimag; --sll 4; -- -4
WHEN "111101" =>
full_range_real_out(16 downto 3) <= fftreal; --sll 3; -- -3
full_range_imag_out (16 downto 3)<= fftimag; --sll 3; -- -3
WHEN OTHERS =>
END CASE;
end if;
END PROCESS mux;
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to sign extend say 12 to 16 bits:
data2 <= std_logic_vector(resize(signed(data1),16)); another note: for testing you can test Real and imaginary outputs directly (no need for old Pythogoras)- Mark as New
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The code is complete, could you please verify if this is correct?
mux:PROCESS(fftexp,fftvalid)
-- VARIABLE sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- sel := s1 & s0; -- concatenate s1 and s0
if (fftvalid = '1') then
CASE fftexp IS
WHEN "110011" =>
full_range_real_out(26 downto 13) <= fftreal ; --sll 13; -- -13
full_range_real_out(12 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 13) <= fftimag; --sll 13; -- -13
full_range_imag_out(12 downto 0) <= (OTHERS => '0'); --sll 13; -- -13
WHEN "110100" =>
full_range_real_out(26)<=fftreal(13);
full_range_real_out(25 downto 12) <= fftreal; --sll 12; -- -12
full_range_real_out(11 downto 0) <= (OTHERS => '0');
full_range_imag_out(26)<=fftimag(13);
full_range_imag_out(25 downto 12) <= fftimag;-- sll 12; -- -12
full_range_imag_out(11 downto 0) <= (OTHERS => '0');
WHEN "110101" =>
full_range_real_out(26 downto 25) <= fftreal(13) & fftreal(13);
full_range_real_out(24 downto 11) <= fftreal;-- sll 11; -- -11
full_range_real_out(10 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 25) <=fftimag(13) & fftimag(13);
full_range_imag_out(24 downto 11) <= fftimag; --sll 11; -- -11
full_range_imag_out(10 downto 0) <= (OTHERS => '0');
WHEN "110110" =>
full_range_real_out(26 downto 24) <= fftreal(13) & fftreal(13)& fftreal(13);
full_range_real_out(23 downto 10) <= fftreal;-- sll 10; -- -10
full_range_real_out(9 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 24) <=fftimag(13) & fftimag(13)& fftimag(13);
full_range_imag_out(23 downto 10) <= fftimag;-- sll 10; -- -10
full_range_imag_out(9 downto 0) <= (OTHERS => '0');
WHEN "110111" =>
full_range_real_out(26 downto 23) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(22 downto 9) <= fftreal; --sll 9; -- -9
full_range_real_out(8 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 23) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out(22 downto 9) <= fftimag; -- sll 9; -- -9
full_range_imag_out(8 downto 0) <= (OTHERS => '0');
WHEN "111000" =>
full_range_real_out(26 downto 22) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(21 downto 8) <= fftreal; --sll 8; -- -8
full_range_real_out(7 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 22) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out(21 downto 8) <= fftimag; --sll 8; -- -8
full_range_imag_out(7 downto 0) <= (OTHERS => '0');
WHEN "111001" =>
full_range_real_out(26 downto 21) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(20 downto 7) <= fftreal; --sll 7; -- -7
full_range_real_out(6 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 21) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out (20 downto 7)<= fftimag; --sll 7; -- -7
full_range_imag_out(6 downto 0) <= (OTHERS => '0');
WHEN "111010" =>
full_range_real_out(26 downto 20) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(19 downto 6) <= fftreal; --sll 6; -- -6
full_range_real_out(5 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 20) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out (19 downto 6) <= fftimag; --sll 6; -- -6
full_range_imag_out(5 downto 0) <= (OTHERS => '0');
WHEN "111011" =>
full_range_real_out(26 downto 19) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(18 downto 5) <= fftreal; --sll 5; -- -5
full_range_real_out(4 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 19) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out(18 downto 5) <= fftimag; --sll 5; -- -5
full_range_imag_out(4 downto 0) <= (OTHERS => '0');
WHEN "111100" =>
full_range_real_out(26 downto 18) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(17 downto 4) <= fftreal; --sll 4 -- -4
full_range_real_out(3 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 18) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out(17 downto 4) <= fftimag; --sll 4; -- -4
full_range_imag_out(3 downto 0) <= (OTHERS => '0');
WHEN "111101" =>
full_range_real_out(26 downto 17) <= fftreal(13) & fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13)& fftreal(13);
full_range_real_out(16 downto 3) <= fftreal; --sll 3; -- -3
full_range_real_out(2 downto 0) <= (OTHERS => '0');
full_range_imag_out(26 downto 17) <=fftimag(13) & fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13)& fftimag(13);
full_range_imag_out (16 downto 3)<= fftimag; --sll 3; -- -3
full_range_imag_out(3 downto 0) <= (OTHERS => '0');
WHEN OTHERS =>
END CASE;
end if;
END PROCESS mux;
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--- Quote Start --- to sign extend say 12 to 16 bits: data2 <= std_logic_vector(resize(signed(data1),16)); another note: for testing you can test Real and imaginary outputs directly (no need for old Pythogoras) --- Quote End --- I did'nt see you're comment in time. I now have done it manually
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So Kaz, now I got these 2 huge vectors with the FFT's scaled real and imaginary data in. Now I have to Pythagoras them, right? But as what kind of format do I have to look at them?
Is it now an signed integer?- Mark as New
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--- Quote Start --- So Kaz, now I got these 2 huge vectors with the FFT's scaled real and imaginary data in. Now I have to Pythagoras them, right? But as what kind of format do I have to look at them? Is it now an signed integer? --- Quote End --- yes once you do the scaling the values are signed 2's complement as input. The output practically should not be that wide and you will need to observe the exponent as to what range is practical for your case then do some trimming on bits to fit fewer bits. You don't need to square it up to amplitude, you might just check each of real and imaginary directly.
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I just put the real vector on the leds of the DE-1 board en saw that when I put music in, the leds are getting a bit nervous. This is a good thing I think. However, if I put our old Greek in. Amplitudes are the same af they were before scaling but now just a larger number.
Mind you, the only way I can test this is putting the result on the LEDs of the board because I have no Opencore IP license to do it in Modelsim.
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