Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
Hi, i am having this error and I don't know how to fix it, I have to finish this for today for my school and I do not know what to do.
Error (10170)...
17268 Discussions
Hi, i am having this error and I don't know how to fix it, I have to finish this for today for my school and I do not know what to do.
Error (10170): Verilog HDL syntax error at ctrl.v(170) near text: "assign"; expecting an operand.
You have to supply the verilog source code line(s) that are being flagged or no one is going to be able to help you in any reasonable way. Just the error message(s) are not enough.
When you right click on the error message, you can cross probe to a chrome/IE to provide the error message explanation. If this message is not clear, let us know. We will try to make better explanation on it.
