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JFrye7
Beginner
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Hooking up Mentor AXI BFM to Platform Designer Simulation

I have a platform designer system where I have a Mentor Graphics AXI3 Master. I have successfully created the test bench system, but when I go to run the simulation script (either in ModelSim-Altera with the generated script ./testbench/mentor/msim_setup.tcl) or in the tool when I point to the test bench file, set it as top, and include the rest of the files in the simulation/submodules directory, it complains that it cannot find the module named mgc_axi_master_0, which is the name assigned to the generated Mentor Graphics AXI3 Master in the platform designer. How can I make sure this RTL si generated then also plug into the API to generated AXI-3 transactions to program slaves on the AXI/Avalon bus?

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Have you Generate VHDL simulation and synthesis files for your system? Which Quartus version are you using? (pro / standard)

You can try to go through the simulation flow and check is there anything amiss.

Reference (pro): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf

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