currently i am trying to generate a custom component with the Component Editor. I am developing for a Cyclone V E board and use Quartus version 19.1 Lite Edition.
My issue : after adding my VHDL files to the Synthesis list, analyzing them, and setting a top level modul, no interfaces or signals are recognized.
I figured out the programm does not recognize STD_ULOGIG, only STD_LOGIC. Is there any Workaround for this, i.e. settings or lines of code i can add to the top level to tell the editor, that it shall use my ULOGIC port?
Thank you guys in advance
From this article, it sounds like you just have to add the interfaces and ports manually: