Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15469 Discussions

How To Avoid GND Synthesized As Routed Net?

JLevi1
Beginner
820 Views

I have a net that is getting synthesized as a fixed logic '0' value and then routed to 900+ logic element endpoints in the design. This net is named "~GND" and does not exist in the Verilog source code. I would like to change that to a local fixed value instead so that I can clear up many routing lanes to improve the timing performance of the design.

 

The source code for one 8-bit counter that uses this ~GND net sets some of the counter bits to '1' and some of the counter bits to '0' as can be shown in the source code snippet below:

lpm_counter new_trig ( .aclr(reset_in), .cout(new_trig_cout), .cnt_en(!new_trig_out[7]), .clock(clk_sensor_out), .data(8'b01010101), .sload(rst_cvc_pulse), .q(new_trig_out[7:0]) ); defparam new_trig.lpm_width = 8, new_trig.lpm_direction = "DOWN";

In the resulting synthesized version of this counter, the counter bits that are preset to '1' get a local fixed value, but the counter bits that are preset to '0' get connected to this ~GND net as shown in the screen capture below.

Has anybody else had this happen in the synthesis? If so, is there a way to get force the synthesis tool to use a local fixed value instead of routing a net with a fixed value?

 

Thanks!

John

0 Kudos
3 Replies
JLevi1
Beginner
108 Views

I referred to a screen shot on the previous post. I pasted the screen shot into the post but I see that it disappeared in the final version of my post. I will attempt to paste the screen shot image in this second post.

 

JLevi1
Beginner
108 Views

Hmm, pasting the screenshot into the forum post is not working for me. I cannot see the image using Firefox browser. I could see the screenshot fine before submitting but then it disappears after submitting. As a result, I am attaching the screenshot image to his 3rd post as a file.

Abe
Valued Contributor II
108 Views

Whenever you hardcode any port/signal / register to a fixed value, the compiler will either tie the signals in question to VCC or GND or ~GND. This cannot be avoided. The other way is to have a register with this value and then connect this register to the port/signal in question. But you are just moving the VCC/GND tie to another level.

Reply