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How avoid registers or wires are removed (by the optimizator) for creating small delays?

MauroChim
Beginner
198 Views

I'm new with the quartus software and now i'm fighting with a very simple problem.

I need to create some clocks skews adding some ports as little delays, but i'm not able to to avoid the optimizer remove all my addictive ports , so i'm not able to add any timing shifts.

How can I control that?  i tried unckeck all optimizations available, but always all wires and registers are removed.

For example to be able to use this module:

// ****************

module my_delay_line(s_in ,s_out);
  parameter n=20;
  genvar i;
  input s_in;
  output s_out;
  wire [n-1:0] delay;
  assign s_out=delay[n-1];
  assign delay[0] = ~s_in;
  generate
      for (i=0; i<n-1; i=i+1)
        begin: generate_delay
        assign delay [i+1] = ~delay [i ];
        end
  endgenerate
endmodule

// ********************

Thank you.

0 Kudos
2 Replies
SyafieqS
Moderator
175 Views

How you tried to use noprune to preserve the register? or turn off the optimization setting in Quartus (will affect timing) ?


  1. https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_preserv...

SyafieqS
Moderator
158 Views

We do not receive any response from you to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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