I'm new with the quartus software and now i'm fighting with a very simple problem.
I need to create some clocks skews adding some ports as little delays, but i'm not able to to avoid the optimizer remove all my addictive ports , so i'm not able to add any timing shifts.
How can I control that? i tried unckeck all optimizations available, but always all wires and registers are removed.
For example to be able to use this module:
module my_delay_line(s_in ,s_out);
wire [n-1:0] delay;
assign delay = ~s_in;
for (i=0; i<n-1; i=i+1)
assign delay [i+1] = ~delay [i ];
How you tried to use noprune to preserve the register? or turn off the optimization setting in Quartus (will affect timing) ?
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