How do I add the 'altera_merlin_slave_translator' to my Quartus 20.2 Platform Designer?

[MSenk1]

Hallo,

I'm using Quartus 20.2. In my design in the Platform Designer I would like to add the 'altera_merlin_slave_translator'. I can find it in the 'intel_fpga_pro/ip/altera/...  but not in the IP Catalog.

So how can I add it to my design?

regards

Mike

[sstrell]

There is no need to manually add this component into a system design.  It is automatically added into the interconnect as needed when you generate the system.  What are you trying to do?

#iwork4intel

[MSenk1]

Thank you,

I learnt that I have to use the Avalon_clock_crossing_bridge instead of the older 'slave_translator'.

I had to generate my own read_data_valid, but finally it works.

A hint in the documentation that the older 'merlin' based connectors are replace by the Avalon_clock_crossing_bridge would have help a lot.

Thanks

Mike