How do I check the delay of a combinational design?

[PEgan]

For a project I have built a complex multiplier which performs 37x37 signed multiplication using the cyclone IV's built in 18x18 multipliers. I have also added additional adders and logic which may make the delay longer than my clock cycle using the 50MHz clock. I have skimmed over the Timing Analyzer software briefly but do not know if this is overkill for what I'm trying to test. Ideally, I just want a simple solution to see the delay to perform a full complex calculation using my IP.

[sstrell]

Timing analysis with the Timing Analyzer is a hugely important aspect of FPGA design, so it's a good idea to become familiar with the process and the tool. For all designs, you should create at least a basic .sdc (timing constraints) file that defines the clocks in your design and your I/O timing requirements. With that, you can then run the tool to see if your design will meet the requirements.

There's a lot to take in on this, and it can seem overwhelming, but I recommend starting with this timing analysis training that walks through the basics of the tool and .sdc files:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

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