How do I disable setup/hold violation errors?

[Altera_Forum]

I'm simulating a design with ModelSim-Altera. The design has two clock domains and I'm using two-stage synchronizers on data that crosses between the clock domains. Because the two clocks are close in frequency but not equal I get a huge number of setup and hold violations on the synchronizer FFs, which is to be expected. Is there a way to disable setup and hold violations in the Altera simulation libraries?

[Altera_Forum]

You can just skip timing analysis for transfers between asynchronous clock domains. In your .sdc file either put clocks in separate clock groups or set false path between them. For example: 

set_clock_groups -asynchronous -group -group or set_false_path -from -to set_false_path -from -to

[Altera_Forum]

I already did that. This takes care of SDC but doesn't fix the problem with the post-fit simulation.

[Altera_Forum]

false paths in sdc means just that at any level. It must you got something else violating timing. I suggest you use fifo instead of your two stage synchroniser.

[Altera_Forum]

A FIFO isn't an appropriate solution. The problem isn't with the design, which works fine in real hardware. This is purely a simulation annoyance. A FIFO wont do anything anyway, since internally the FIFO uses the same synchronization chain mechanism.

[Altera_Forum]

I am not sure about your description, which tool is reporting tSU/tH violation. Is it Modelsim or quartus? 

 A fifo does have synchroniser similar to yours but plus handshaking logic to cross data correctly across both domains.

[Altera_Forum]

It's ModelSim I'm using for the simulation.

[Altera_Forum]

Does Modelsim report tSU/tH timing violation?

[Altera_Forum]

No modelsim does simulation and doesn't do a timing a violation as a error. I may be corrected though by someone else but this is my observation

[Altera_Forum]

TrueBlue,  

after you start simulation, you need to use the tcheck_set command to disable the timing checks on the first level of synchronizer FFs.