I have relatively simple design using logic only, no SOC or NIOS or hard processor. I need to Instantiate the internal PLL and Reset monitor, can I do this manually or do I need to use Platform designer. Likewise I can not find the documentation on how to set / place / use I/O blocks at the pin. I need to have an I2C controller with bidirectional I/O pin. does the tool automatically place things to I/O logic cells based on design constraints, or do I have to manually do this?
In the main Quartus Prime software, you access IP, like a PLL, from the IP Catalog. You generate the IP, which includes instantiation templates which simplifies instantiating the IP into your HDL code.
As for I/O, after performing at least Analysis & Elaboration (first stage of synthesis), you can open the Pin Planner from the Assignments menu to make I/O assignments.
I am using a max 10 fpag, with external pin DEV_CLRn is disabled in prime tool and there is no external pullup or pulldown, so how do I attach to the DEV_CLRn signal, is this signal internally generated inside the device, or will it get synthesized out because the tool setting has the pin disabled on the Max10->Device->Device and Pin Options->General-> unchecked "Enable device - wide reset (DEV_CLRn) is unchecked. how does the device come out of reset, do i still have an internal device_reset signal generated by an internal RC type circuit? IF so how do I instantiate or connect to that signal???
Articles on what DEV_CLRn does:
Your design itself should have some type of reset control.
Yes I see a very small window open with very limited IP. There is no IP for connection to Global Reset. where is the documentation for the device level instantiation, you know the stuff that used to be called "Primitives" the old Altera specific general purpose IP that you can manually instantiate. like clock buffers, and I/O cells, and Global Device Reset, and the like, or am I supposed to somehow get the tool to do all this for me using the platform designer, which seems total over kill to create a system with nothing but a reset circuit and a clock buffer. I found and am using the PLL
I'm not quite sure what you are referring to. Are you thinking about what you would add in a schematic design? The clock control block IP is essentially a clock buffer, and I/O cells are not manually added to a design as an IP other than in a schematic (and you would still need to go to the Pin Planner to create I/O assignments). And I've never heard of a global device reset IP.
If you're creating an HDL design (not using Platform Designer), you create a top-level design in Verilog, SystemVerilog, or VHDL. You can create IP from the IP catalog and then instantiate that IP in your HDL code using the instantiation template generated by the IP Parameter Editor.
I am Farabi who will be supporting this request.
As Sstrell mentioned, If you're creating an HDL design (not using Platform Designer), you create a top-level design in Verilog, SystemVerilog, or VHDL. You can create IP from the IP catalog and then instantiate that IP in your HDL code using the instantiation template generated by the IP Parameter Editor.
Dev_CLRn pin is an external pin which supposed to be controlled by external IO or some other microcontrollers. It can't be controlled from inside the FPGA. So in top level schematic, this pin will be connected to external IOs.
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