Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

ISSP in Quartus

sidd
Novice
1,433 Views

I am using Quartus lite V20.1 with max V CPLD. Can ISSP be used with this?

Does it require a license version?

 

If it works then facing following issue with ISSP:

I tried with Quartus lite V 20.1 and max V CPLD. After adding ISSP, in compilation report I can see LEs being consumed for ISSP. But ISSP editor is giving error as "No instances found in the current project or on the device"  Need help.

 

Also any other debugging technique to simulate inputs and check outputs on CPLD?

 

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sstrell
Honored Contributor III
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If Quartus lets you add the ISSP IP and compile your design in Lite, then it is supported.

Are you programming the device in the .spf file or using the Quartus Programmer?  Make sure in the .spf file you have selected the programming cable (USB blaster) and the device.

You can also try Signal Tap.

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sidd
Novice
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I am using USB blaster II here with .pof file. 
Do I have to use .pof or .svf file? @sstrell 

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sstrell
Honored Contributor III
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You should be programming the device with a .sof or .pof file and you need an active JTAG connection to the device.  I don't know what a .svf file is.

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sidd
Novice
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I am programing with .pof file and I have a active JTAG connection. 

Using .pof file quartus shows flashing successful.

 

As flash can be done through programmer window as well as In systems and sources and probe editor.

from both places I am able to flash using .pof file. 

 

but after flashing through In systems and sources and probe editor, its is showing "No instances found in the current project or on the device" .

 

If I am able to flash through USB blaster does that not mean I have a active JTAG connection? or there is something else?

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sstrell
Honored Contributor III
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Hmm.  Double-check that you've instantiated the ISSP IP correctly and that the nets you are connecting to have not been optimized away for some reason.  Check the Compilation report too to see that the on-chip debugging tool has been included in the compiled design.  Check that IP that includes the name "sld" (system level debug) has been added to your project hierarchy.  This is the JTAG hub that allows a JTAG connection into the device to access on-chip debugging tools.

If it still doesn't work, MAX V may not be supported, but I don't see why it would let you add the IP to a MAX V design if it wasn't supported.

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AR_A_Intel
Employee
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Thanks for your update answer @sstrell. We have not heard from you and hope the last note clears up this matter. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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