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Hello, i am a newbie, and having verilog counter code. I don`t know how to add "counter" as a NEW CUSTOM Qsys components?
module counter_qsys ( out , // Output of the counter clk , // clock Input ); input clk; output [7:0] out; reg [7:0] out=0; //-- Sensitive to rising edge always @(posedge clk) begin //-- Incrementar el registro out <= out+1; end endmodule In qsys, i have clicked NEW component, and i got one pop-window. But in block "out" port is missing. I dont whether i am doing right or wrong. Please anyone guide me.Link Copied
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You have to go through the Component Editor and make your component Avalon compatible. See online training:
https://www.altera.com/support/training/course/oqsys3000.html https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=reusable- Mark as New
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--- Quote Start --- You have to go through the Component Editor and make your component Avalon compatible. See online training: https://www.altera.com/support/training/course/oqsys3000.html https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=reusable --- Quote End --- Hi, I have followed that link. But i didnt see tutorial or any videos. That link page states about the course.
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You have to register for the training (Register Now link at the bottom).
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