How to add top level generic into a Qsys system?

[gyuunyuu]

Some custom VHDL components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the generic value. The Qsys system is instantiated in a VHDL testbench and BFMs are connected to it. I want to be able to change their value from outside Qsys, in my VHDL testbench.

Is there a way to create generic at Qsys system level and then be able to change their value when the Qsys system is instantiated in my VHDL testbench? These "top level" generics will directly connect to generics on the custom Qsys system components' top level.

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to passing the generics from top level to your custom component in a Qsys system. To facilitate further debugging, would you mind to share with me a simple test design which demonstrate the issue encounter with generic passing?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[gyuunyuu]

See, I basically want to know, how to add generic to a Qsys system itself. I could just open the generated top level .vhd file of the Qsys system and add them there. However, when the system is regenerated, they shall be lost.

[CheePin_C_Intel]

Hi,

My understanding is that the Qsys generated top level .vhd file should have the generics. I might be wrong. Would you mind to share with me your .qsys file so that I could replicate the observation? I might need to further engage with Factory in case there are generics in the Qsys system but the generated top level .vhd file does not have it.

I believe the workaround currently would be as you mentioned, manually add them in the Qsys generated top level .vhd file while we are looking into it to avoid gating your progress.

Thank you.

[CheePin_C_Intel]

It would be great if you could share with me a simple test design QAR.

[gyuunyuu]

The zip file contains following things:

1. .vhd file for a custom Qsys component
2. _hw.tcl file for item in (1)
3. .qsys file of a system where (1) has been instantiated
4. the generated simulation and synthesis files

If you look at the generated simulation and synthesis entity top level, you will find that it has no generics and only ports.

I can open Qsys and change the values of the generics. But, Qsys does not have option to provide access to these generics in the top level entity.

I can of course just modify the code by hand and add generics to the simulation and synthesis top level entities. But these shall be lost when the system is generated again.

In summary, the qsys_component.vhd has:

generic ( counter_max: integer range 15 to 65535 := 15; write_address: std_logic_vector(31 downto 0) := (others=>'0') );

I want that the top level entity of Qsys system expose these as well. The top level entity is qsys_system.vhd.

[gyuunyuu]

Dear cphan, I uploaded some files onto the forum yesterday, which you can use to understand the problem. Regards, Hassan Iqbal

[CheePin_C_Intel]

Hi,

Thanks for sharing the files. I am currently looking into it and will update you on the progress by mid of next week. please ping me if you do not hear back from me. Thank you.

[CheePin_C_Intel]

Hi,

Sorry for any confusion. For your information, as I look into the qsys_system.vhd (which I believe is the top level of Qsys HDL file) inside folder qsys_system\synthesis\, I am able to find the generics for qsys_component as following. Would you mind to further elaborate on the specific generic that you are looking for if it is something different from the existing?

"

 component qsys_component is

  generic (

   counter_max  : integer                      := 15;

   write_address : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"

  );

  port (

   clk              : in std_logic                    := 'X'; -- clk

   reset_n          : in std_logic                    := 'X'; -- reset_n

   avm_write        : out std_logic;                           -- write

   avm_write_data   : out std_logic_vector(31 downto 0);       -- writedata

   avm_write_address : out std_logic_vector(7 downto 0);        -- address

   avm_wait_request : in std_logic                    := 'X' -- waitrequest

  );

 end component qsys_component

"

Please let me know if there is any concern. Thank you.

Chee Pin

[gyuunyuu]

Dear cpchan, I want that the generics that exist on the qsys_component are exposed in the qsys_system. In other words, entity qsys_system is port ( clk_clk : in std_logic := '0'; -- clk.clk reset_reset_n : in std_logic := '0' -- reset.reset_n ); end entity qsys_system; Should become: entity qsys_system is generic ( counter_max : integer := 15; write_address : std_logic_vector(31 downto 0) := "00000000000000000000000000000000" ); port ( clk_clk : in std_logic := '0'; -- clk.clk reset_reset_n : in std_logic := '0' -- reset.reset_n ); end entity qsys_system; In this way, I can access and change the generic passed to the componet when I instantiate the Qsys system in my VHDL RTL code. Is the question clear now? Regards, Hassan Iqbal

[CheePin_C_Intel]

Hi,

Thanks lot for your clarification. As I understand it, you would like Qsys to be able to allow setting/exporting of subcomponent generics up to the qsys_system level. This is so that when you instantiate the qsys_system as a submodule to another top level, you are able to pass the generics from top level to qsys_system and down to the Qsys sub component. 

If my understanding is correct, as I discussed with my peers, it seems like currently this is something not supported by Qsys. As a workaround, you might need to manually edit the qsys_system.vhd file to export the generics. Sorry for the inconvenience. I will look into filing enhancement on this for future software release.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[gyuunyuu]

Dear cpchan, Yes, you understood the problem correctly. Its just that when manually editing Qsys files, the changes are lost when we regenerate the system. Regards, Hassan Iqbal

[CheePin_C_Intel]

Hi Hassan,

I can understand the pain of the manual work. Sorry for the inconvenience. Please use the workaround of manual editing due to limitation with Qsys currently.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

I believe the initial enquiry in this case has been addressed and I will set this to close-pending for the moment. Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[gyuunyuu]

I did not know that an SR had been created for this. If you have filed for an improvement to the factory, I guess that is all that can be done. Maybe sometime in the future, many years from now, I will see it.

[CheePin_C_Intel]

Hi,

Sorry for any confusion. For your information, I was required to close the case from my side in the server. Sorry if the previous post has created any confusion. Enhancement has been filed for Factory to look into. Sorry for the inconvenience.