How to apply set_disable_timing SDC command before synthesis?

[NuvKFC]

I have a path, Cell|in to Cell|out, want to disable by using set_disable_timing like follows.

set_disable_timing -from dataa to combout Cell

After Fitter, I can find the signal in on the dataa, and the signal out on the combout.

So, I can use the "set_disable_timing -from dataa to combout Cell" to disable the timing path.

But before synthesis, how to know that the signal in is on the dataa?

Thanks

[FvM]

Usually timing analysis is performed from/to registers or ports, not for individual logic cells on the path. When you cut a logic cell, you cut the whole path. Why not simply specify a timing exception between pre-synthesis entities? What do you want to achieve?

[NuvKFC]

Thank you, FvM, very, very, mhuch.

My purpose is for ASIC verification.

The design's architecture is as follows picture.

There are 2 clocks that pass the mux logic which is controlled by test signal.
I want to break the timing on node A or the timing path from node A to mux|out. 


Due to unsupported set_case_analysis command, I try to use set_disable_timing command to do this.

Unfortunately, I don't know that the node A is on the dataa, datab, datac, datad, datae, or dataf before synthesis.

And I had tried to set_false_path command, but it can't work on a clock path.
Ex. set_false_path -from PLL/clock -through mux|out. (The mux|out node is CLK in the above picture.)

[sstrell]

I don't quite understand why you want to cut timing on a clock path, but what you should be looking at is using set_clock_groups, not set_false_path, to indicate that only one clock domain is active on the output of the mux at a time:

set_clock_groups -exclusive -group {PLL_out} -group {PLL_outdiv4}

[NuvKFC]

Thank you, sstrell, very, very, much.

Yes, you are right.

However, the node A only work under that Test is 1 which is one kind of test mode.

On the FPGA, we don't verify that test mode.
So,  I want to break the timing arc on the node A  to reduce resource cost and compiler time. 

I can't find a way to do that expect for modifying RTL code. 

[NuvKFC]

And there are the other case about output clock on the pad.

The PAD A have 2 functions.
One is the data path from Function A.
The other one is the clock path from Function B.

If I create a generated clock for CLK B on the PAD A, that clock will go into Function A.
So, Function A will have two clocks, the generated clock on the PAD A and PLL output.

However, the clock of Function A,  the clock of Function B, and the generated clock on the PAD A are in the same clock domain.
I need take many many effort to set false path between the generated clock on the PAD A and the Function A.

So, I want to stop the clock propagating of the generated clock on the PAD A into the Function A.

Unfortunately, I don't know where is the Node C before synthesis when use the set_disable_timing command.

[ShengN_Intel]

Hi,

Means that you possible to see node c after synthesis? Probably can include node c in sdc after synthesis. Or using wildcard.

I believe sdc constraints like set_disable_timing will be processed at timing analysis stage.

Thanks,

Regards,

Sheng

[NuvKFC]

Thank you, ShengN, very, very, mhch.

No, I get a problem. Sorry about that.

I'm a Quartus GUI user. 
Before getting off work, I click start compilation. Then next day, I can check the result.

However, "start compilation" button will continuous do Synthesis, Fitter, Timequest, and Assembler.

The next day, I only can see the result that after Fitter.
So, I only can find the "cell|datac" where is the node c location in the Chip Planner after Fitter.

Could you please tell me how to find the specified node after Synthesis?.

[ShengN_Intel]

Hi,

After full compilation, put the respective node name in your case "cell|datac" to the sdc command set_disable_timing. Then re-run the compilation again to load sdc file, does it helps?

Thanks,

Regards,

Sheng

[NuvKFC]

Compiler twice!

I get it.

Maybe it can work. I think it should work.

Thank you, ShengN, very, very, much.

[ShengN_Intel]

Hi,

Let me know if you still have any further concern or update from your side.

Thanks,

Regards,

Sheng

[NuvKFC]

Thank you, ShengN, very, very, much.

I have no concern now.
I'm a GUI user. 
I get a experience that TCL user may be more convenience.

I will try to get the node C or that signal after synthesis.

Do you know any SDC command to meet it?

I only know the  get_cell and the get_pins command.

[Kenny_Tan]

reopening the case.

[ShengN_Intel]

Hi,

You may check this link https://www.intel.com/content/www/us/en/docs/programmable/683432/24-2/tcl_pkg_sdc_ver_1-5.html

get_cells (::quartus::sdc)

get_clocks (::quartus::sdc)

get_nets (::quartus::sdc)

get_pins (::quartus::sdc)

get_ports (::quartus::sdc)

and this link https://www.intel.com/content/www/us/en/docs/programmable/683432/24-2/tcl_pkg_sdc_ext_ver_2-0.html

get_active_clocks (::quartus::sdc_ext)

get_fanins (::quartus::sdc_ext)

get_fanouts (::quartus::sdc_ext)

get_keepers (::quartus::sdc_ext)

get_nodes (::quartus::sdc_ext)

get_partitions (::quartus::sdc_ext)

get_registers (::quartus::sdc_ext)

Let me know if you have any further concern or update.

Thanks,

Regards,

Sheng