I assigned internal signals to pins on the FPGA by using the Signal Probe debug tool. I then saved the changes which runs the fitter. The fitter failed to fit route the requested signal the requested pin. The error said that the signal pin is 3.3V but that the bank 5 voltage is 1.8V.
Only in the pin planner I created a new name and assigned it to the pin location where I want Signal Probe to route the signal. I the also set the I/O standard to same as other pins in the bank 5, bank 5 has EMIF pins.
I have following questions:
Please find my response below: