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Hi,
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ? The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ? How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ? Do you have, please, any documentation about it ? Thank you.Link Copied
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Documentation can be found on the OpenCL Programming Guide which details how to setup the XML and to create an RTL library to be used in OpenCL
https://www.altera.com/en_us/pdfs/literature/hb/opencl-sdk/aocl_programming_guide.pdf#_opentopic_toc_processing_d116e26845- Mark as New
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Hi,
Please refer to this example below, https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-design-example.html Regards, CloseCL (This message was posted on behalf of Intel Corporation)
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