Hi,
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ?
The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ?
How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ?
Do you have, please, any documentation about it ?
Thank you.
