Hi,
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ? The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ? How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ? Do you have, please, any documentation about it ? Thank you.Link Copied
Documentation can be found on the OpenCL Programming Guide which details how to setup the XML and to create an RTL library to be used in OpenCL
https://www.altera.com/en_us/pdfs/literature/hb/opencl-sdk/aocl_programming_guide.pdf#_opentopic_toc...Hi,
Please refer to this example below, https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-desi... Regards, CloseCL (This message was posted on behalf of Intel Corporation)For more complete information about compiler optimizations, see our Optimization Notice.