How to compress or reduce the binary size to the equivalent of an old FPGA

[TK0312]

When I was designing on Cyclone1, the binary size was within 64KB in compressed mode.
When I compiled the exact same design file on Cyclone10LP, the binary size grew to more than 160KB in compressed mode.
Is there any way to keep the binary size within 64KB?
Is it possible to reduce the size by doing some optimization?

Cyclone1 : EP1C6
Cyclone10LP : 10CL016

[FvM]

Hi,
I'm quite sure it's not possible.

1. Uncompressed EP1C6 image is specified with 146 kB, compression factor isn't necessarily better than 60 %, even compressed image isn't guaranteed to fit 64 kB.

2.Uncompressed 10CL016 image is 509 kB, a fully utilized device needs > 256 kB fpr compressed image.

My approach is to reserve space for unmcompressed configuration image if possible. 

[WZ2]

Hello,

In the binary file, there is a section that represents the device netlist, which is the customer logic implemented in the FPGA circuit. Therefore, the more complex the device, the more complex this section becomes. In other words, the configuration file for different devices are not comparable.

For a binary file, the compressed mode is already the smallest and FPGA-recognizable mode.

Best regards,

WZ