How to configure the PCIe Hard IP block on a Stratix V GX FPGA Development Kit using Quartus.

[JWrig25]

I have been trying to configure the IP block for PCIe on my Stratix V GX FPGA and I was following along the steps in this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01097-1.3.pdf on page 2-3 which goes through the process of configuring the Hard IP through the MegaWizard Manager. I have followed all the steps in the process but whenever I try and compile the design in Quartus, I get the error: Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. I don't know why the design is not fitting on the Stratix FPGA when the design used and the process is all design specifically for Stratix V GX FPGA boards.

[BoonT_Intel]

Hi Sir,

For the SV kit, you can use this reference design and see it fit correctly.

https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/an-690-pci-express-dma-reference-design-for-stratix-v-devices/

[JWrig25]

Hi, I have tried to click on the documentation for that example but after I agree to the terms and conditions nothing happens. No files get downloaded. There doesn't seem to be any other relevant information on that site, I have tried the tutorial and that does not work either. I thought the issue might be my internet connection but I have tried two different wifi sources and the website does not load anything for either of them. Is there something I am missing? Thanks.

[BoonT_Intel]

Hi Here is the link to documentation:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an690.pdf