How to constrain the outputs of a Cyclone V ALTLVDS_TX (timing)

Altera_Forum · ‎12-09-2015

Hi everyone,

I'm working on an FPGA design with a Cyclone V SoC driving a DAC at 250MS/s (dual-channel, one channel on clock high, one on clock low). The FPGA is speed grade I7, but TimeQuest complained about timing violations when using the simple DDR outputs (ALTDDIO_OUT). This made me switch to the ALTLVDS_TX buffers with a serialization factor of 4. Except for the fact that I need to invert the first bit (MSB ) of each stream, this seems to work. But now the whole thing has real timing problems even though TimeQuest is happy with at least 400ps slack. It somehow works when the FPGA is actively cooled, but starts to generate completely bogus data after running a few minutes without forced airflow (heatsink temperature rises to some 60°C or so). And all this is very depending on the fitter settings. It works better if I tell the fitter that the device temperature will be only 0°C..85°C than when the industrial range (-40..100) is set. Which is quite counterintuitive to me, as I'd expect the design to perform better when it has to support a larger temperature range.

One problem may be that my outputs to the DAC are not constrained for timings. How do I need to do this? There are other threads in this forum which give me the idea that no timing constraints are required because there is fixed dedicated hardware anyway. Is this really true? What about the optional I/O delays, will they always be the same for all outputs if not explicitly assigned differently?

I'd really be glad if someone could shed some light on this. Thanks!

Best regards,

Philipp

Altera_Forum · ‎01-15-2016

Ok, this issue is fixed now. In the original design, all the logic including the SERDES was clocked directly from an input pin. Now I have inserted a PLL with a 1:1 one clock ratio and it works. Strange...

Regards,

Philipp