How to define clock generated by the other clock?

[Altera_Forum]

Supposed we have CLKA = 100MHz. 

Then we generate CLKB = 200MHz based on CLKA, pls see the following picture: http://blogimg.chinaunix.net/blog/upfile2/080109103218.jpg   In TimeQuest, how to define CLKB? The phase shift between CLKA & CLKB is based on fitting result, so they are unrelated clocks, right? And so I should cutting the path analysis between them?

[Altera_Forum]

I think Altera talks about this in the following doc: 

 http://www.altera.com/literature/hb/qts/qts_qii53019.pdf   on page 7-19. By default the two clocks will be considered related in TimeQuest. If the circuit is designed such that they are assumed unrelated, then a false path can be assigned between them.

[Altera_Forum]

Sorry, the web link seem to be damaged. 

Pls check it. If possible, could send me the datasheet to my mail box directly: CaiWG.NiosII@gmail.com  Thanks again!

[Altera_Forum]

Hi, I have found the related info in QuartusII 7.1 handbook. 

In fact, I have read it before, but I can't find any answer for my question above.  Just for the simple question above, could you answer directly, I'm a little confused.    --- Quote Start ---  The phase shift between CLKA & CLKB is based on fitting result, so they are unrelated clocks, right? And so I should cutting the path analysis between them?  --- Quote End ---    I myself think that: Thouth the phase shift between CLKA & CLKB is based on fitting result, but TimeQuest should also know the phase shift, so it should create tge generated clock automatically.   Thanks...

[Altera_Forum]

Isn't that a divide-by-2, not a multiply-by-2, circuit that you showed? CLKB will be half the frequency (twice the period) of CLKA. 

    --- Quote Start ---  I myself think that: Thouth the phase shift between CLKA & CLKB is based on fitting result, but TimeQuest should also know the phase shift, so it should create tge generated clock automatically.  --- Quote End ---    Yes, TimeQuest knows the delay the register and routing creates between CLKA and CLKB, but TimeQuest does not know the effect on the frequency. You use a generated clock for CLKB to tell TimeQuest how to compute the CLKB frequency from the upstream CLKA frequency. You do not specify a phase shift--TimeQuest adds a clock network delay automatically.  Do not use a circuit like this if you still have a PLL available to create CLKB. Another option is to use a divide-by-2 clock enable instead of a derived clock.  If you do create a clock with logic this way, be aware of the caveats in my posts at http://www.alteraforum.com/forum/showthread.php?t=754. As discussed in my first post in that thread, it is OK if CLKB uses global routing, you set up your design so that no data paths between the CLKA and CLKB domains are synchronous, and you use set_false_path or set_clock_groups to cut analysis on the cross-domain data paths.

[Altera_Forum]

David, 

 I am not sure if anybody gave you the actual answer to your specific question. The answer is very simple: CLKA and CLKB are in fact related, and should not be cut unless you have a specific reason to do so (like a FIFO to synch up the transfer). The delay between CLKA and CLKB is modeled as clock latency (both by TimeQuest and Classic). So, all you need to do is:   create_clock -period 10 CLKA  create_generated_clock -divide 2 -source CLKA CLKB  TimeQuest will then do everything right. If you want to then see the details of the analysis, remember to use "-detail full_path" when running report_timing. That will show you the delays between CLKA and CLKB.  You can see the example at:  http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html

[Altera_Forum]

great answer!! 

That is what I want. Wow, I get a big fish again, the more important is I get two fishing technologies. :) I always think that fishing is much more important than fishes.  Thanks all of you & altera forum from my deep heart!

[Altera_Forum]

I am just thinking the following question: 

Why I can't find such important info from Altera's handbook directly, it's very important for newers, isn't it?

[Altera_Forum]

I have the similar situation, but CLKB is not connected to FPGA pin: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8239  Quartus 12.1 gives Warning (332060): Node: inst33 was determined to be a clock but was found without an associated clock assignment.  What should be done to get rid of this warning?  What associated clock assignment should be set in .sdc file for CLKB?  P.S.  Example at Figure 1. "Divide by 2 Generated Clock" ( create_generated_clock_ex1.qar (http://www.altera.com/support/examples/download/create_generated_clock_ex1.qar) ) in the above mentioned Altera document http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html after being compiled produces the same  Warning (332060): Node: div2reg was determined to be a clock but was found without an associated clock assignment.

[Altera_Forum]

Hi to everyone. Unfortunately i am a new guy and i have recently started using the FPGAs. I have also the same problem which is how to get double output frequency from an input clock. Unfortunately i have tried also this method and the results are that in my case i can really double the frequency but the problem that i now face is that i cannot make a clear pulse around 50 % Duty cycle. Any idea if is this possible. The frequency input of my system is only 10 MHz and the target frequency is 20MHz which are generally considered to be small frequencies. Please has anyone any idea on how to achieve it? I have attached a picture of the circuits i made and botha work without the desired duty cycle. 

 (PS* i use only the schematic designs without knowing anything from Verilog or VHDL) :(

[Altera_Forum]

Generating clocks like the above is a very bad idea. For a start no one corrects the OP on his fundamental mistake that ClkB is actually CLKA/2, not CLKA x2.  

But generating clocks with logic for anything except slow frequencies (like < 1MHz) will be prone to timing variations from different compilations, high fanout skew, temperature fluctuation. Basically, everything you cannot control.  You should use a PLL to generate any clocks, as you have full control over phase, fanout skew will be close to 0 and it will not vary with temperature. And you will get a 50% duty cycle. So Use a PLL (available in the megawizard).

[Altera_Forum]

Thanks a lot for your answer. In the Altera Max 2 Kit is given the possibility to use a digital PLL named as 72497 and can be found easily at the Library others/maxplus2/74297. The fact is that using this chip is a bit difficult for me because i actually see many Pins and it's a bit terrifying to me. I have still downloaded the datasheets of the 74297 but there are still many issues and many things such as Phase 1 , Phase 2 , Phase B and so on....Any friendly advice with that?

[Altera_Forum]

An "all digital" PLL like 74297 can only generate a time-discrete output signal with transitions at the input clock active edge. I guess, it's not what you imagine as a PLL clock generator. To learn about 74297 function, you can refer to the datasheet and application notes of the respective TTL IC. 

 To multiply a clock frequency, generate rational frequency ratios and phase shifted clocks, you need an analog VCO as part of the PLL design. It's provided e.g. with most FPGA, but not with MAX II. Altera once advertised a PLL block for MAX V series, but it hasn't been seen in operation yet, apparently it dropped behind the event horizon... http://www.alteraforum.com/forum/showthread.php?t=27399

[Altera_Forum]

The Problem i face is that the circuit i have attached before produces the frequency i need but not with the correct duty cycle. It is something that i have already measured with the oscilloscope. I repeat that the circuit works but the pulse i get Needs to have a duty cycle at 50 %. Unfortunately the duty cycle seems to be not ok so i do not know if there is a digital way using only gates flip Flops or whatever so that i will not have to Change the development board. But also if things are not so good and there is no possibility to use a digital pll then is there any way to use Phase delays somehow? Regarding the 74297 obviously is not the solution i was looking for so....Keep searching...

[Altera_Forum]

The reason that i insist trying to produce 20 Mhz this way is that i want to make the circuit completely digital because i have already the solution using an analog circuit....And of course it is better than the analog solution.

[Altera_Forum]

You didn't post a circuit, but I guess it's a delay chain with XOR gate. This "poor man's" frequency doubler will hardly have a symmetrical duty cycle.

[Altera_Forum]

It's almost exactly like the circuit of the first Person who opened this Topic. A good solution is the one that is already answered but the fact is that, it cannot run to my web Edition quartus because the message i get is that it is for the statix 2 Family... My aim is to simulate that using my max2 kit and i think that it will not work in my case....

[Altera_Forum]

--- Quote Start ---  It's almost exactly like the circuit of the first Person who opened this Topic.  --- Quote End ---   The circuit divides a clock by two. You asked to double a clock frequency which can be hardly achieved by this circuit.   Please clarify.

[Altera_Forum]

Hi again, i have the circuit attached in a pdf file. The Problem with it is that i cannot get the desired duty cycle.

[Altera_Forum]

O.K. that's a different version of the said "poor man's" frequency doubler.  

 I'm not sure if usage of toggle FF instead of a pure logic cell delay line changes much to the basic behaviour, except for a slightly larger delay. To get a 20 MHz output with roughly symmetrical duty cycle, you need 25 ns delay, I guess about 50 to 100 logic cells of MAX II. In HDL, you need a keep synthesis attribute to prevent elimination of the redundant logic cells during synthesis. Don't know how it works in schematic entry. The main disadvantage of logic cell delay chains is their sensitivity to PVT (process, voltage, temperature) variations. The expectable minimum and maximum delay (fast and slow "corner") have an about 1:2 ratio, a designed duty cycle of 50% could be 35 or 70% as well.

[Altera_Forum]

Thanks a lot for the help...You mentioned something which has to do with the hdl. You probably mean vhdl. The circuit i have is a bit bigger than the one i have already shown you so and i do not know anything from vhdl....So a possible solution is to apply that kind of method in order to achieve it...Correctly?