How to define clock generated by the other clock?

[Altera_Forum]

Supposed we have CLKA = 100MHz. 

Then we generate CLKB = 200MHz based on CLKA, pls see the following picture: http://blogimg.chinaunix.net/blog/upfile2/080109103218.jpg   In TimeQuest, how to define CLKB? The phase shift between CLKA & CLKB is based on fitting result, so they are unrelated clocks, right? And so I should cutting the path analysis between them?

[Altera_Forum]

In this case HDL means VHDL or Verilog.  

 I assume that the circuit can be described with schematic entry, too. I just said, I don't know how you instruct Quartus not to remove redundant logic cells.   I see that you can use a lcell logic symbol. Shown with only 4 logic cells. You need at least 30.