Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16556 Discussions

How to design a 1-out-of-3 clock multiplex

OCn
Novice
549 Views

Hi!
I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL.
Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. And, I can't cascade two altclkctrl because its input can only be clock pin or PLL's ouput clock.
I'm wondering if there is any way I can design a 1-out-of-3 clock multiplex?

Here is my configuration:
Terasic DE3 (Stratix III) + Quartus 13.1

0 Kudos
1 Solution
4 Replies
JonWay_C_Intel
Employee
528 Views

Perhaps you can consider implementing it in the core logic.

You can refer to: https://courses.cs.washington.edu/courses/cse467/08au/labs/Resources/Recommended%20HDLCoding%20Styles.pdf

Page 56.

You will need to evaluate if this works for you.

 

 

0 Kudos
OCn
Novice
524 Views

Hi JonWay,

Thanks for your reply and suggestion.

That Verilog code's function should be OK. And, how should I ensure that the output clock will use the global clock network, as that clock will drive a lot of circuit in our design?

 

0 Kudos
JonWay_C_Intel
Employee
523 Views
0 Kudos
OCn
Novice
518 Views

Hi JonWay,

OK, I understand.

Thanks for your prompt reply and help!

I wish you a good day!

 

0 Kudos
Reply