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OCn
Novice
140 Views

How to design a 1-out-of-3 clock multiplex

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Hi!
I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL.
Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. And, I can't cascade two altclkctrl because its input can only be clock pin or PLL's ouput clock.
I'm wondering if there is any way I can design a 1-out-of-3 clock multiplex?

Here is my configuration:
Terasic DE3 (Stratix III) + Quartus 13.1

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JonWay_C_Intel
Employee
113 Views
4 Replies
JonWay_C_Intel
Employee
119 Views

Perhaps you can consider implementing it in the core logic.

You can refer to: https://courses.cs.washington.edu/courses/cse467/08au/labs/Resources/Recommended%20HDLCoding%20Style...

Page 56.

You will need to evaluate if this works for you.

 

 

OCn
Novice
115 Views

Hi JonWay,

Thanks for your reply and suggestion.

That Verilog code's function should be OK. And, how should I ensure that the output clock will use the global clock network, as that clock will drive a lot of circuit in our design?

 

JonWay_C_Intel
Employee
114 Views
OCn
Novice
109 Views

Hi JonWay,

OK, I understand.

Thanks for your prompt reply and help!

I wish you a good day!

 

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