I am following AN756 to try to implement a source-synchronous output interface (Arria 10, Quartus 21.3 Pro):
The lower block shows "Reference Clock from Core or from Dedicated Clock In Pin". However, a "core" (PLL-generated) clock failed to build... and eventually I found this explanation:
Starting with Quartus Prime software version 17.0, the “Use core PLL reference clock connection” is no longer visible in the Arria 10 Altera PHYLite IP parameter editor.
To enable the “Use core PLL reference clock connection” (Quartus Prime software version 17.0 and later), please add the below INI in the quartus.ini file.
ip_altera_phylite_en_pll_core_ref_ck = on
My first problem is I'm not sure where to find "quartus.ini". The closest thing I could find is quartus2.ini, which is located in the %USERPROFILE% directory (in Windows 10).
However, when I add the commands to that file, nothing seems to change. I have tried putting the commands in different places in the quartus2.ini file, changing to uppercase, changing whitespace, rebooting my PC, but nothing seems to work. I don't see any new option appear in Platform Designer:
and the build still fails with the same error:
How can I make this work?
Please create a text file named quartus.ini in the folder where your Quartus project is present. You can then add the suggested lines to that file.